Description
The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information.
Features
- pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects. Using National Semiconductor’s proprietary random lock, the Serializer’s parallel data are randomized to the Deserializer without the need of REFCLK. n Supports AC-coupling data transmission n Individual power-down controls for both Transmitter and Receiver n 1.8V VCM at LVDS input side n Embedded clock CDR (clock and data recovery) on Receiv.
DS90UR124 Datasheet
