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DS90CR564 - LVDS 18-Bit Color Flat Panel Display FPD Link

Download the DS90CR564 datasheet PDF. This datasheet also covers the DS90CR563 variant, as both devices belong to the same lvds 18-bit color flat panel display fpd link family and are provided as variant models within a single manufacturer datasheet.

Description

The DS90CR563 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams.

A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (DS90CR563_NationalSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
DS90CR561 18-Bit Color Flat Panel Display Link Texas Instruments
DS90CR562 18-Bit Color Flat Panel Display Link Texas Instruments
DS90CR583 LVDS Texas Instruments
DS90CR584 LVDS Texas Instruments
DS90CR215 +3.3V Rising Edge Data Strobe LVDS Texas Instruments

Other Datasheets by National Semiconductor (Texas Instruments)

Part Number Description
DS90CR561 LVDS 18-Bit Color Flat Panel Display Link
DS90CR562 LVDS 18-Bit Color Flat Panel Display Link
DS90CR563 LVDS 18-Bit Color Flat Panel Display FPD Link
DS90CR581 LVDS Transmitter 24-Bit Color Flat Panel Display Link
DS90CR583 LVDS 24-Bit Color Flat Panel Display Link

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DS90CR563/DS90CR564 LVDS 18-Bit Color Flat Panel Display (FPD) Link— 65 MHz July 1997 DS90CR563/DS90CR564 LVDS 18-Bit Color Flat Panel Display (FPD) Link— 65 MHz General Description The DS90CR563 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CR564 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel.