DS32EL0124 Datasheet | National Semiconductor

Description The DS32EL0124/DS32ELX0124 integrates clock and data recovery modules for high-speed serial munication over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly .. interface. The DS32EL0124/DS32ELX0124 deserializes up to 3.125 Gbps of high speed serial data to 5 LVDS outputs without the need for an external reference clock. With DC-balance decoding enabled, the application payload of 2.5 Gbps is deserialized to 4 LVDS outputs. The DS32EL0124/DS32ELX01214 deserializers feature a remote sense capability to automatically signal link status conditions to its panion DS32EL0421/ELX0421 serializers without requiring an additional feedback path. The parallel LVDS interface of these devices reduce FPGA I/O pins, board trace count and alleviates EMI issues, when pared to traditional single-ended wide bus interfaces. The DS32EL0124/ELX0124 is programmable through a SMBus interface as well as through control pins. Features - - - - - - - - - - - - - - - - - 5-bit LVDS parallel data interface Programmable Receive Equalization Selectable DC-balance decoder Selectable De-scrambler Remote Sense for automatic detection and negotiation of link status No external receiver reference clock required LVDS parallel interface Programmable LVDS output clock delay Supports output data-valid signaling Supports keep-alive clock output On chip LC VCOs Redundant serial input (ELX device only) Retimed serial output (ELX device only) Configurable PLL loop bandwidth Configurable via SMBus Loss of lock and error reporting 48-pin LLP package with exposed DAP Applications - - - - - - Imaging: Industrial, Medical Security, Printers Displays: LED walls, mercial Video Transport munication Systems Test and Measurement Industrial Bus Key Specifications - - - - - - 1.25 to 3.125 Gbps serial data rate 125 to 312.5 MHz DDR parallel clock -40° to +85°C temperature...