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DM74LS164 - 8-Bit Serial In/Parallel Out Shift Registers

General Description

These 8-bit shift registers feature gated serial inputs and an asynchronous clear A low logic level at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock pulse thus providing complete control over incoming data A high logic level on either i

Key Features

  • Y Gated (enable disable) serial inputs Y Fully buffered clock and serial inputs Y Asynchronous clear Y Typical clock frequency 36 M.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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54LS164 DM54LS164 DM74LS164 8-Bit Serial In Parallel Out Shift Registers June 1989 54LS164 DM54LS164 DM74LS164 8-Bit Serial In Parallel Out Shift Registers General Description These 8-bit shift registers feature gated serial inputs and an asynchronous clear A low logic level at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock pulse thus providing complete control over incoming data A high logic level on either input enables the other input which will then determine the state of the first flip-flop Data at the serial inputs may be changed while the clock is high or low but only information meeting the setup and hold time requirements will be entered Clocking occurs on the low-to-high level transition of the clock input All inpu