DM54S195 registers equivalent, 4-bit parallel access shift registers.
Y Synchronous parallel load Y Positive-edge-triggered clocking Y Parallel inputs and outputs from each flip-flop Y Direct overriding clear Y J and K inputs to first stage.
These 4-bit registers feature parallel inputs parallel outputs J-K serial inputs shift load control input and a direct overriding clear All inputs are buffered to lower the input drive requirements The registers have two modes of operation
Parallel (.
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