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National Semiconductor Electronic Components Datasheet

CS5535 Datasheet

I/O Companion Multi-Function South Bridge

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Preliminary
July 2003
Revision 0.8
Geode™ CS5535 I/O Companion
Multi-Function South Bridge
General Description
The National Semiconductor® Geode™ CS5535 is a com-
plete I/O companion for an integrated processor North
Bridge component such as the Geode GX2 processor
series. Together, the GX2 and CS5535 provide a system-
level solution well suited for the high-performance and low-
power needs of a host of information appliances that
include digital set-top boxes, personal access devices, and
thin client applications.
The internal architecture has been greatly simplified over
previous I/O companions by use of a single, high-perfor-
mance modular structure based on GeodeLink™ architec-
ture. This architecture yields high internal speed (over 4
GB/s) data movement and extremely versatile internal
power management. The GeodeLink architecture is trans-
parent to application software. Communication with the
GX2 processor is over a 33/66 MHz PCI bus.
The CS5535 incorporates many I/O functions, including
those found in typical SuperI/O chips, simplifying many
system designs. Since the graphics subsystem is entirely
contained in the GX2 processor, system interconnect is
simplified. The device contains state-of-the-art power man-
agement that enables systems, especially battery powered
systems, to significantly reduce power consumption.
Audio is supported by an internal controller, designed to
connect to multiple AC97 compatible codecs such as
National’s LM4550. An IR (infrared) port supports all popu-
lar IR communication protocols. The IR port is shared with
one of two industry-standard serial ports that can reach
speeds of 115.2 kbps. An LPC (low pin count) port is pro-
vided to facilitate connections to a SuperI/O should addi-
tional expansion, such as a floppy drive, be necessary,
and/or to an LPC ROM for the system BIOS.
Geode™ CS5535 Block Diagram
Test/Reset
Interface
GeodeLink™ Control
Processor (GLCP)
External USB
Ports 1-1 & 1-2
USB Controller #1
(USBC1)
External USB
Ports 2-1 & 2-2
USB Controller #2
(USBC2)
External
Audio
AC97 Controller
(ACC)
External
IDE/Flash
ATA-5 Controller
(ATAC)
System Power
Voltages
Low Voltage
Detect (LVD)
Power Good
for Power On
Reset (POR)
GeodeLink™
Interface
Unit
(GLIU)
Geode™ GX2 Interface
PCI
33 or 66 MHz
GeodeLink™ PCI
South Bridge
(GLPCI_SB)
Diverse Integration Logic (DIVIL)
82xx PC
Legacy
Flash
Interface
RTC &
CMOS RAM
Diverse
Device (DD)
UART (2)
& IR (1)
SMB
Controller
LPC
Port
GPIO
Power
Mgmnt
MFGP
Timers
National Semiconductor and Virtual System Architecture are registered trademarks of National Semiconductor Corporation.
Geode, GeodeLink, MacPHYTER, WebPAD, and VSA are trademarks of National Semiconductor Corporation.
For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks.
© 2003 National Semiconductor Corporation
www.national.com


National Semiconductor Electronic Components Datasheet

CS5535 Datasheet

I/O Companion Multi-Function South Bridge

No Preview Available !

General Description (Continued)
The hard disk controller is an ATA-5 compatible bus mas-
tering IDE controller; includes support for two ATA-compli-
ant devices on one channel. Two dual-port USBs (universal
serial buses, USB specification v1.1 compliant) provide
four ports with both low and full-speed capabilities for Plug
& Play expansion for a variety of consumer peripheral
devices such as a keyboard, mouse, printer, and digital
camera. A battery-backed RTC (real-time clock) keeps
track of time and provides calendar functions.
A suite of 82xx devices provide the legacy PC functionality
required by most designs, including two PICs (programma-
ble interrupt controllers), one PIT (programmable interval
timer) with three channels, and DMA (direct memory
access) functions. The CS5535 contains eight MFGPTs
(multi-function general purpose timers) that can be used for
a variety of functions. A number of GPIOs (general purpose
input/outputs) are provided, and are assigned to system
functions on power-up (i.e., LPC port); each of these may
be reassigned and given different I/O characteristics such
as debounce, edge-triggering, etc.
State-of-the-art power management features are attained
with the division of the device into two internal power
domains. The GPIOs and multi-function timers are distrib-
uted into each of the two domains to allow these to act as
wakeup sources for the device. In addition to full ACPI
(Advanced Configuration Power Interface) compliance and
support of industry-standard Wakeup and Sleep modes,
the device automatically disables clocks from internal
blocks when they are not being used.
Features
General Features
Designed for use with National’s Geode GX2 processor
series
208-Terminal PBGA (plastic ball grid array) package
3.3V I/O and 1.5V (nominal) Core operation
Low power operation: less than 1.0W in Working state
Working and Standby power domains
IEEE 1149.1 compliant TAP and boundary scan
GeodeLink PCI Bridge (South Bridge)
Provides a PCI interface for GeodeLink devices:
— PCI specification v2.2 compliant
— 32-Bit, 33/66 MHz operation
— Transaction FIFOs (first in/first out)
— Bus master or slave
— Converts selected PCI configuration bus cycles to
internal MSR (Model Specific Register) cycles
— Capable of handling in-bound transactions immedi-
ately after reset - no setup
— Mapping of PCI virtual configuration space to MSR
space is done completely in VSA™ (Virtual System
Architecture®) code
— Serialized processor control interface
GeodeLink Control Processor
SUSP#/SUPA# handshake with power management
logic provides Sleep control of all GeodeLink devices
System software debug support using built-in “logic
analyzer” with:
— 8192-bit capture memory
— Capture memory can be organized wide or narrow
— “Analyzer” can be connected to thousands of
possible internal nodes
— Synchronous operation with GX2 GeodeLink Control
Processor
— JTAG interface and system bus interfaces
— For debug use, able to conduct any GeodeLink trans-
action via the JTAG interface
— Manufacturing test support
ATA-5 Controller
66 MB per second IDE Controller in UDMA mode per
the ATA-5 specification
3.3V interface
Legacy and Enhanced PIO (Programmable I/O),
MDMA (Multi DMA), and UDMA (Ultra DMA) modes
One channel with two devices
Multiplexed with Flash interface
Flash Interface
Multiplexed with IDE interface
Connects to array of industry standard NAND Flash
and/or NOR Flash
NOR optional execute-in-place boot source
NAND optional file system
General purpose ISA bus slave-like devices supported
with configurable chip selects
Hardware support for SmartMedia type ECC (Error
Correcting Code) calculation off loading software inten-
sive algorithm
USB Controllers 1 and 2
Two independent host USB controllers; doubles the
throughput of a single controller
Each controller has two ports; total of four ports
USB specification v1.1 compliant, with external crimp
protection diodes
OHCI (Open Host Controller Interface) specification v1.0
compliant
Supports wakeup events
Second generation proven core design
Over-current and power control support
GeodeLink master burst reads and writes
www.national.com
2
Revision 0.8


Part Number CS5535
Description I/O Companion Multi-Function South Bridge
Maker National Semiconductor
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CS5535 Datasheet PDF






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