CD4035BC Datasheet | National Semiconductor

Description The CD4035B 4-bit parallel-in parallel-out shift register is a monolithic plementary MOS (CMOS) integrated circuit constructed with P- and N-channel enhancement mode transistors This shift register is a 4-stage clocked serial register having provisions for synchronous parallel inputs to each stage and serial inputs to the first stage via JK logic Register stages 2 3 and 4 are coupled in a serial ‘‘D’’ flipflop configuration when the register is in the serial mode (parallel serial control low) Parallel entry via the ‘‘D’’ line of each register stage is permitted only when the parallel serial control is ‘‘high’’ In the parallel or serial mode information is transferred on positive clock transitions When the true plement control is ‘‘high’’ the true contents of the register are available at the output terminals When the true plement control is ‘‘low’’ the outputs are the plements of the data in the register The true plement control functions asynchronously with respect to the clock signal JK input logic is provided on the first stage serial input to minimize logic requirements particularly in counting and sequence-generation applications With JK inputs connected together the first stage bees a ‘‘D’’ flip-flop An asynchronous mon reset is also provided Features Y Y Y Y Y Y Y Y Y Wide supply voltage range 3 0V to 15V High noise immunity 0 45 VDD (typ ) Low power TTL Fan out of 2 driving 74L patibility or 1 driving 74LS 4-stage clocked operation Synchronous parallel entry on all 4 stages JK inputs on first stage Asynchronous true plement control on all outputs Reset control Static flip-flop operation master slave configuration Buffered outputs Low power dissipation 5 m W (typ ) (ceramic) High speed to 5 MHz Applications Automotive Data terminals Instrumentation Medical electronics Alarm systems Industrial controls Remote metering puters Logic Diagram TL F 5964 - 1 P S e 0 e serial mode T C e 1 e true outputs TG e transmission...