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CD4027BC - Dual J-K Master/Slave Flip-Flop

Description

These dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and Pchannel enhancement mode transistors Each flip-flop has independent J K set reset and clock inputs and buffered Q and Q outputs These flip-flops are edge sensitive to the clock input and ch

Features

  • Y Y Y Y Y Wide supply voltage range High noise immunity Low power TTL compatibility Low power Medium speed operation 3 0V to 15V 0 45 VDD (typ ) Fan out of 2 driving 74L or 1 driving 74LS 50 nW (typ ) 12 MHz (typ ) with 10V supply Schematic and Connection Diagrams TL F 5958.
  • 1 Dual-In-Line Package Order Number CD4027B TL F 5958.
  • 2 Top View C1995 National Semiconductor Corporation TL F 5958 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Note 1 and 2) If Mi.

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CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset February 1988 CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset General Description These dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and Pchannel enhancement mode transistors Each flip-flop has independent J K set reset and clock inputs and buffered Q and Q outputs These flip-flops are edge sensitive to the clock input and change state on the positive-going transition of the clock pulses Set or reset is independent of the clock and is accomplished by a high level on the respective input All inputs are protected against damage due to static discharge by diode clamps to VDD and VSS Features Y Y Y Y Y Wide supply voltage range High noise immunit
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