National Semiconductor Electronic Components Datasheet

CD4027BC Datasheet

Dual J-K Master/Slave Flip-Flop with Set and Reset

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February 1988

CD4027BM CD4027BC Dual J-K Master Slave

Flip-Flop with Set and Reset

General Description

These dual J-K flip-flops are monolithic complementary

MOS (CMOS) integrated circuits constructed with N- and P-

channel enhancement mode transistors Each flip-flop has

independent J K set reset and clock inputs and buffered

Q and Q outputs These flip-flops are edge sensitive to the

clock input and change state on the positive-going transition

of the clock pulses Set or reset is independent of the clock

and is accomplished by a high level on the respective input

All inputs are protected against damage due to static dis-

charge by diode clamps to VDD and VSS

Features

Y Wide supply voltage range

Y High noise immunity

Y Low power TTL

compatibility

Y Low power

Y Medium speed operation

3 0V to 15V

0 45 VDD (typ )

Fan out of 2 driving 74L

or 1 driving 74LS

50 nW (typ )

12 MHz (typ )

with 10V supply

Schematic and Connection Diagrams

Dual-In-Line Package

TL F 5958 – 1

Order Number CD4027B

Top View

C1995 National Semiconductor Corporation TL F 5958

TL F 5958 – 2

RRD-B30M105 Printed in U S A

National Semiconductor Electronic Components Datasheet

CD4027BC Datasheet

Dual J-K Master/Slave Flip-Flop with Set and Reset

No Preview Available !

Absolute Maximum Ratings (Note 1 and 2)

If Military Aerospace specified devices are required

please contact the National Semiconductor Sales

Office Distributors for availability and specifications

DC Supply Voltage (VDD)

b0 5 VDC to a18 VDC

Input Voltage (VIN)

b0 5V to VDD a0 5 VDC

Storage Temperature Range (TS)

b65 C to a150 C

Power Dissipation (PD)

Dual-In-Line

700 mW

Small Outline

500 mW

Lead Temperature (TL)

(Soldering 10 seconds)

260 C

Recommended Operating

Conditions (Note 2)

DC Supply Voltage (VDD)

3V to 15 VDC

Input Voltage (VIN)

0V to VDD VDC

Operating Temperature Range (TA)

CD4027BM

CD4027BC

b55 C to a125 C

b40 C to a85 C

DC Electrical Characteristics CD4027BM (Note 2)

Symbol

Parameter

Conditions

b55 C

a25 C

a125 C

Units

Min Max Min Typ Max Min Max

IDD

VOL

VOH

Quiescent Device Current VDD e 5V VIN e VDD or VSS

VDD e 10V VIN e VDD or VSS

VDD e 15V VIN e VDD or VSS

1 30 mA

2 60 mA

4 120 mA

Low Level

Output Voltage

lIOl k 1 mA

VDD e 5V

VDD e 10V

VDD e 15V

0 05

0 0 05

0 05 V

High Level

Output Voltage

lIOl k 1 mA

VDD e 5V

VDD e 10V

VDD e 15V

4 95

9 95

14 95

4 95

9 95

14 95

4 95

9 95

14 95

VIL Low Level

Input Voltage

VDD e 5V VO e 0 5V or 4 5V

VDD e 10V VO e 1V or 9V

VDD e 15V VO e 1 5V or 13 5V

15 15 V

30 30 V

40 40 V

VIH High Level

Input Voltage

VDD e 5V VO e 0 5V or 4 5V

VDD e 10V VO e 1V or 9V

VDD e 15V VO e 1 5V or 13 5V

11 0

35 V

70 V

11 0 V

IOL Low Level Output

Current (Note 3)

VDD e 5V VO e 0 4V

VDD e 10V VO e 0 5V

VDD e 15V VO e 1 5V

0 64 0 51 0 88

1 6 1 3 2 25

42 34 88

0 36 mA

0 9 mA

2 4 mA

IOH High Level Output

Current (Note 3)

VDD e 5V VO e 4 6V

VDD e 10V VO e 9 5V

VDD e 15V VO e 13 5V

b0 64

b1 6

b4 2

b0 51 b0 88

b1 3 b2 25

b3 4 b8 8

b0 36

b0 9

b2 4

IIN Input Current

VDD e 15V VIN e 0V

VDD e 15V VIN e 15V

b0 1

b10b5 b0 1

10b5 0 1

b1 0 mA

1 0 mA

Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the devices

should be operated at these limits The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device

operation

Note 2 VSS e 0V unless otherwise specified

Note 3 IOH and IOL are tested one output at a time

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CD4027BC Datasheet

Dual J-K Master/Slave Flip-Flop with Set and Reset

CD4027BC Datasheet

Dual J-K Master/Slave Flip-Flop with Set and Reset

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