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CD40174BM - Hex/Quad D Flip-Flop

General Description

The CD40174B consists of six positive-edge triggered D-type flip-flops the true outputs from each flip-flop are externally available The CD40175B consists of four positiveedge triggered D-type flip-flops both the true and complement outputs from each flip-flop are externally available All flip-flops

Key Features

  • Y Y Y Y Y Wide supply voltage range 3V to 15V High noise immunity 0 45 VDD (typ ) Low power TTL fan out of 2 driving 74L compatibility or 1 driving 74 LS Equivalent to MC14174B MC14175B Equivalent to MM74C174 MM74C175 Connection Diagrams CD40174B Dual-In-Line Package CD40175B Dual-In-Line Package TL F 5987.
  • 1 TL F 5987.
  • 2 Top View Order Number CD40174B or CD40175B Top View Truth Table Inputs Clear L H H H H H L X NC e e e e e e Outputs D X H L X X Q L H L NC NC Q H L H.

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📁 Similar Datasheet

Part Number Description Manufacturer
CD40174BM CMOS HEX D-TYPE FLIP-FLOP Texas Instruments
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CD40174B CMOS HEX D-TYPE FLIP-FLOP Texas Instruments
CD40174B CMOS HEX D-TYPE FLIP-FLOP RCA
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Other Datasheets by National Semiconductor (Texas Instruments)

Part Number Description
CD40174BC Hex/Quad D Flip-Flop
CD40175BC Hex/Quad D Flip-Flop
CD40175BM Hex/Quad D Flip-Flop
CD4017BC Decade Counter/Divider
CD4017BM Decade Counter/Divider

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CD40174BM CD40174BC Hex D Flip-Flop CD40175BM CD40175BC Quad D Flip-Flop February 1988 CD40174BM CD40174BC Hex D Flip-Flop CD40175BM CD40175BC Quad D Flip-Flop General Description The CD40174B consists of six positive-edge triggered D-type flip-flops the true outputs from each flip-flop are externally available The CD40175B consists of four positiveedge triggered D-type flip-flops both the true and complement outputs from each flip-flop are externally available All flip-flops are controlled by a common clock and a common clear Information at the D inputs meeting the set-up time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse The clearing operation enabled by a negative pulse at Clear input clears all Q outputs to logical ‘‘0’’ and Qs (CD40175B o