n Clock enable for address and data synchronization applications n Eight edge-triggered D flip-flops n Buffered common clock n See ’FCT273 for master reset version n See .

n Eight edge-triggered D flip-flops n Buffered common clock n See ’FCT273 for master reset version n See ’FCT373 for tra.

The ’FCT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The sta.

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