NT5DS32M16CG Overview
Key Specifications
Operating Voltage: 2.6 V
Max Voltage (typical range): 2.7 V
Min Voltage (typical range): 2.5 V
Length: 12 mm
Description
Die C of 512Mb SDRAM devices based using DDR interface. They are all based on Nanya’s 90 nm design process.
Key Features
- DDR 512M bit, Die C, based on 90nm design rules
- Double data rate architecture: two data transfers per clock cycle
- Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
- DQS is edge-aligned with data for reads and is centeraligned with data for writes
- Differential clock inputs (CK and CK)
- Four internal banks for concurrent operation
- Data mask (DM) for write data
- DLL aligns DQ and DQS transitions with CK transitions
- Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
- Burst lengths: 2, 4, or 8
Representative NT5DS32M16CG image (package may vary by manufacturer)
