NT5DS128M4CS Overview
Die C of 512Mb SDRAM devices based using DDR interface. They are all based on Nanya’s 90 nm design process. The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits.
NT5DS128M4CS Key Features
- DDR 512M bit, Die C, based on 90nm design rules
- Bidirectional data strobe (DQS) is transmitted and
- DQS is edge-aligned with data for reads and is centeraligned with data for writes
- Differential clock inputs (CK and CK)
- Four internal banks for concurrent operation
- Data mask (DM) for write data
- DLL aligns DQ and DQS transitions with CK transitions
- mands entered on each positive CK edge; data and
- Burst lengths: 2, 4, or 8
- CAS Latency: 2.5, 3