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NT5DS128M4CS - 512Mb DDR SDRAM

Download the NT5DS128M4CS datasheet PDF. This datasheet also covers the NT5DS32M16CG variant, as both devices belong to the same 512mb ddr sdram family and are provided as variant models within a single manufacturer datasheet.

Description

Die C of 512Mb SDRAM devices based using DDR interface.

They are all based on Nanya’s 90 nm design process.

The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits.

Features

  • DDR 512M bit, Die C, based on 90nm design rules.
  • Double data rate architecture: two data transfers per clock cycle.
  • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver.
  • DQS is edge-aligned with data for reads and is centeraligned with data for writes.
  • Differential clock inputs (CK and CK).
  • Four internal banks for concurrent operation.
  • Data mask (DM) for write data.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (NT5DS32M16CG-NanyaTechology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number NT5DS128M4CS
Manufacturer Nanya Techology
File Size 2.15 MB
Description 512Mb DDR SDRAM
Datasheet download datasheet NT5DS128M4CS Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
NT5DS16M16ES Commercial and Industrial Consumer DDR 256Mb SDRAM Nanya
NT5DS16M8AW (NT5DSxxMxAx) 128Mb DDR333/300 SDRAM Nanya Technology
NT5DS32M4AW (NT5DSxxMxAx) 128Mb DDR333/300 SDRAM Nanya Technology
NT5DS32M8AT 256Mb DDR333/300 SDRAM Nanya
NT5DS32M8AW (NT5DSxxMxAx) 256Mb DDR333/300 SDRAM Nanya

Other Datasheets by Nanya Techology

Part Number Description
NT5DS128M4CG 512Mb DDR SDRAM
NT5DS128M4AF (NT5DSxxMxAF) 512Mb DDR SDRAM
NT5DS128M4BF (NT5DSxxMxBx) 512Mb DDR SDRAM
NT5DS128M4BG (NT5DSxxMxBx) 512Mb DDR SDRAM
NT5DS128M4BS (NT5DSxxMxBx) 512Mb DDR SDRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
NT5DS32M16CG NT5DS64M8CG NT5DS128M4CG NT5DS32M16CS NT5DS64M8CS NT5DS128M4CS 512Mb DDR SDRAM Features • DDR 512M bit, Die C, based on 90nm design rules • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for reads and is centeraligned with data for writes • Differential clock inputs (CK and CK) • Four internal banks for concurrent operation • Data mask (DM) for write data • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Burst lengths: 2, 4, or 8 • CAS Latency: 2.
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