NT5DS16M16ES Key Features
- JEDEC DDR pliant
- Differential clock inputs (CK and )
- DLL aligns DQ and DQS transition with CK transitions
- 2n Prefetch Architecture
- DQS is edge-aligned with data for reads and center-aligned with data for WRITEs
- DQ and DM referenced to both edges of DQS
- tRAS lockout (tRAP = tRCD)
- Signal Integrity
- Configurable DS for system patibility
- Data Integrity
