NT5CC256M8FN datasheet, sdram equivalent, Nanya

Features and benefits

* JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM
* Signal Integrity -.

Application

The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and address inputs are syn.

Description

The 2Gb Double-Data-Rate-3 (DDR3(L)) is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAMs. The 2Gb chip is organized as 32Mbit x 8 I/Os x 8 banks or 16Mbit x 16 I/Os x 8 bank devices. T.

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