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PCKEP14 Datasheet

2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver

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PCKEP14
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2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver
Rev. 01 — 30 October 2002
Product data
1. Description
The PCKEP14 is a low skew 1-to-5 differential driver, designed with clock distribution
in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input
signals can be either differential or single-ended (if the VBB output is used). HSTL
inputs can be used when the PCKEP14 is operating under PECL conditions.
The PCKEP14 specifically guarantees low output-to-output skew. Optimal design,
layout, and processing minimize skew within a device, and from device to device.
To ensure that the tight skew specification is realized, both sides of any differential
output need to be terminated identically into 50 resistors, even if only one output is
being used. If an output pair is unused, both outputs may be left open (unterminated)
without affecting skew.
The common enable (EN) is synchronous, outputs are enabled/disabled in the LOW
state. This avoids a runt clock pulse when the device is enabled/disabled, as can
happen with an asynchronous control. The internal flip-flop is clocked on the falling
edge of the input clock, therefore, all associated specification limits are referenced to
the negative edge of the clock input.
The PCKEP14, as with most other ECL devices, can be operated from a positive VCC
supply in PECL mode. This allows the PCKEP14 to be used for high performance
clock distribution in +3.3 V or +2.5 V systems.
2. Features
s 100 ps device-to-device skew
s 25 ps within device skew
s 400 ps typical propagation delay
s Maximum frequency > 2 GHz (typical)
s Contains temperature compensation
s PECL and HSTL mode: VCC = 2.375 V to 3.8 V with VEE = 0 V
s NECL mode: VCC = 0 V with VEE = 2.375 V to 3.8 V
s LVDS input compatible
s Open input default state.


NXP Semiconductors Electronic Components Datasheet

PCKEP14 Datasheet

2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver

No Preview Available !

Philips Semiconductors
3. Pinning information
3.1 Pinning
PCKEP14
2.5 V/3.3 V 1:5 differential ECL/PECwLw/wH.DSaTtLaSchleoectk4Ud.croivmer
Q0 1
Q0 2
Q1 3
Q1 4
Q2 5
Q2 6
Q3 7
Q3 8
Q4 9
Q4 10
20 VCC
19 EN
18 VCC
17 CLK1
16 CLK1
15 VBB
14 CLK0
13 CLK0
12 CLK_SEL
11 VEE
002aaa354
Fig 1. SO20 pin configuration.
Q0 1
Q0 2
Q1 3
Q1 4
Q2 5
Q2 6
Q3 7
Q3 8
Q4 9
Q4 10
20 VCC
19 EN
18 VCC
17 CLK1
16 CLK1
15 VBB
14 CLK0
13 CLK0
12 CLK_SEL
11 VEE
002aaa221
Fig 2. TSSOP20 pin configuration.
3.2 Pin description
Table 1: Pin description
Symbol
Pin
Q0-Q4
1, 3, 5, 7, 9
Q0-Q4
2, 4, 6, 8, 10
VEE
CLK_SEL
11
12
CLK0, CLK1 13, 16
CLK0, CLK1 14, 17
VBB 15
VCC 18, 20
EN 19
Description
Positive ECL/PECL output
Negative ECL/PECL output
Negative supply
ECL/PECL active clock select input. Pin will default LOW
when left open.
ECL/PECL/HSTL CLK input. Pins will default LOW when
left open.
ECL/PECL/HSTL CLK input. Pins will default to VCC/2 when
left open.
Reference voltage output
Positive supply
ECL synchronous enable
3.2.1 Power supply connection
CAUTION
All VCC and VEE pins must be connected to power supply to guarantee
proper operation.
MSC895
9397 750 09565
Product data
Rev. 01 — 30 October 2002
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
2 of 15


Part Number PCKEP14
Description 2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver
Maker NXP Semiconductors
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PCKEP14 Datasheet PDF






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