CBTV4010 Datasheet | NXP Semiconductors

FEATURES - Enable signal is SSTL_2 patible - Optimized for use in Double Data Rate (DDR) SDRAM applications - Designed to be used with 400 Mbps/200 MHz DDR data bus - Switch on resistance is designed to eliminate the need for series resistor to DDR SDRAM - 20 Ω on resistance - Internal 100 Ω pull-down resistors - Low differential skew - Matched rise/fall slew rate - Low cross-talk data-data/data-DQM - Independent DIMM control lines - Latch-up protection exceeds 500 m A per JESD78 - ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 DESCRIPTION This 10-bit bus switch is designed for 2.3 V to 2.7 V VCC operation and SSTL_2 select input levels. Each Host port pin is multiplexed to one of four DIMM port pins. When the S pin is low the corresponding 10-bit bus switch is turned on. The on-state connects the Host port to the DIMM port through a 20 Ω nominal series resistance. When the S pin is high the switch is open and a high-impedance state exists between the two ports. The DIMM port is terminated with a 100 Ω resistor to ground when the S pin is high. The design is intended to have only one DIMM port active at any time. The part incorporates a very low cross-talk design. It has a very low skew between outputs (< 50 ps) and low skew (< 50 ps) for rising and falling edges. The part has optional performance in DDR data bus applications. Each switch has been optimized for connection to 1 or 2-bank DIMMs. The low internal RC time constant of the switch (20 Ω × 7 p F) allows data transfer to be made with minimal propagation delay. The CBTV4010 is characterized for operation from 0 to +85 °C. QUICK REFERENCE DATA SYMBOL t PLH t PHL CIN CON ICCZ PARAMETER Propagation delay An to Yn Input capacitance - control pins Channel on capacitance Total supply current CONDITIONS Tamb = 25 °C; GND = 0 V CL = 7 p F; VCC = 2.5 V VI = 0 V or VCC Vin = 1.5 V VCC = 2.5 V TYPICAL 140 1.8 7 500 UNIT ps p F p F µA ORDERING INFORMATION .....