ADC1115S125 Datasheet | NXP Semiconductors

description The ADC1115S125 is a single channel 11-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power consumption at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1115S125 is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode, thanks to a separate digital output supply. The ADC1115S125 supports the Low Voltage Differential Signalling (LVDS) Double Data Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the user to easily configure the ADC. The device also includes a SPI programmable full-scale to allow flexible input voltage range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more, the ADC1115S125 is ideal for use in munications, imaging and medical applications - especially in high Intermediate Frequency (IF) applications thanks to the integrated input buffer. The input buffer ensures that the input impedance remains constant and low and the performance consistent over a wide frequency range. 2. Features and benefits - SNR, 66.5 d BFS / SFDR, 86 d Bc - Sample rate up to 125 Msps - Input bandwidth, 600 MHz - Power dissipation, 840 m W including analog input buffer - SPI - Duty cycle stabilizer - 11-bit pipelined ADC core - Clock input divider by 2 for less jitter contribution - Integrated input buffer - Fast Ou T of Range (OTR) detection - Flexible input voltage range: 1 V (p-p) to - INL ±1.25 LSB, DNL ±0.25 LSB 2 V (p-p) - CMOS or LVDS DDR digital outputs - Offset binary, two’s plement, gray code - Pin patible with the ADC1415S - Power-down and Sleep modes series, the ADC1215S series and the ADC1015S series - HVQFN40 package NXP Semiconductors ADC1115S125 .. 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 3. Applications -...