Datasheet4U Logo Datasheet4U.com

74LVC3G07 Triple buffer

74LVC3G07 Description

74LVC3G07 Triple buffer with open-drain output Rev.03 * 01 February 2005 www.DataSheet4U.com Product data sheet 1.General .
The 74LVC3G07 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.

74LVC3G07 Features

* s s s s Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: x JESD8-7 (1.65 V to 1.95 V) x JESD8-5 (2.3 V to 2.7 V) x JESD8-B/JESD36 (2.7 V to 3.6 V). ESD protection: x HBM EIA/JESD22-A114-B exceeds

74LVC3G07 Applications

* using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74LVC3G07 provides three non-inverting buffers. The output of the device is an open drain and can be connected to other open-drain outputs to implement active-L

📥 Download Datasheet

Preview of 74LVC3G07 PDF
datasheet Preview Page 2 datasheet Preview Page 3

📁 Related Datasheet

📌 All Tags

Triple buffer NXP Semiconductors
NXP Semiconductors 74LVC3G07-like datasheet