Datasheet4U Logo Datasheet4U.com

74LVC1G175 - Single D-type flip-flop

Description

The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output.

The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input.

Features

  • Wide supply voltage range from 1.65 V to 5.5 V.
  • 5 V tolerant inputs for interfacing with 5 V logic.
  • High noise immunity.
  • Complies with JEDEC standard:.
  • JESD8-7 (1.65 V to 1.95 V).
  • JESD8-5 (2.3 V to 2.7 V).
  • JESD8B/JESD36 (2.7 V to 3.6 V).
  • ESD protection:.
  • HBM JESD22-A114F exceeds 2000 V.
  • MM JESD22-A115-A exceeds 200 V.
  • 24 mA output drive (VCC = 3.0 V).
  • CMOS low power consumption.
  • Latch-up performance exceeds 250 mA.
  • Direct.

📥 Download Datasheet

Datasheet Details

Part number 74LVC1G175
Manufacturer NXP Semiconductors
File Size 146.95 KB
Description Single D-type flip-flop
Datasheet download datasheet 74LVC1G175 Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
74LVC1G175 Single D-type flip-flop nexperia
74LVC1G175-Q100 Single D-type flip-flop NXP
74LVC1G175-Q100 Single D-type flip-flop nexperia
74LVC1G17 Single Schmitt-trigger buffer NXP
74LVC1G17 SINGLE SCHMITT-TRIGGER BUFFER Diodes

Other Datasheets by NXP Semiconductors

Part Number Description
74LVC1G125 Bus buffer/line driver
74LVC1G157 Single 2-input multiplexer
74LVC1G3157 2-channel analog multiplexer/demultiplexer
74LVC1G38 2-input NAND gate
74LVC1G386 3-input EXCLUSIVE-OR gate

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74LVC1G175 Single D-type flip-flop with reset; positive-edge trigger Rev. 6 — 11 October 2013 Product data sheet 1. General description The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.