74HCT03 Datasheet | NXP Semiconductors

FEATURES - Level shift capability - Output capability: standard (open drain) - ICC category: SSI GENERAL DESCRIPTION The 74HC/HCT03 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns 74HC/HCT03 The 74HC/HCT03 provide the 2-input NAND function. The 74HC/HCT03 have open-drain N-transistor outputs, which are not clamped by a diode connected to VCC. In the OFF-state, i.e. when one input is LOW, the output may be pulled to any voltage between GND and VOmax. This allows the device to be used as a LOW-to-HIGH or HIGH-to-LOW level shifter. For digital operation and OR-tied output applications, these devices must have a pull-up resistor to establish a logic HIGH level. TYPICAL SYMBOL t PZL/ t PLZ CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2× fi + ∑ (CL × VCC2 × fo) + ∑ (VO2/RL) × duty factor LOW, where: fi = input frequency in MHz fo = output frequency in MHz VO = output voltage in V CL = output load capacitance in p F VCC = supply voltage in V RL = pull-up resistor in MΩ ∑ (CL × VCC2 × fo) = sum of outputs ∑ (VO2/RL) = sum of outputs 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V 3. The given value of CPD is obtained with: CL = 0 p F and RL = ∞ ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. PARAMETER propagation delay input capacitance power dissipation capacitance per gate notes 1, 2 and 3 CONDITIONS HC CL = 15 p F; RL = 1 kΩ; VCC = 5 V 8 3.5 4.0 HCT 10 3.5 4.0 ns p F p F UNIT December 1990 Philips Semiconductors .. Product specification Quad 2-input NAND gate PIN DESCRIPTION PIN NO. 1, 4, 9, 12 2, 5, 10, 13 3, 6, 8, 11 7 14 SYMBOL 1A to 4A 1B to 4B 1Y to 4Y GND VCC NAME AND FUNCTION data inputs data inputs data outputs ground (0 V) positive supply voltage 74HC/HCT03 Fig.1 Pin...