NXP Semiconductors
PTN3460I
eDP to LVDS bridge for industrial and embedded applications
eDP complying PWM signal generation or PWM signal pass through from eDP source
2.2 DisplayPort receiver features
Compliant to DP v1.2a and v1.1a
Compliant to eDP v1.2 and v1.1
Supports Main Link operation with one or two lanes (select through configuration pin
CFG3, see Table 4 for more details)
Supports Main Link rate: Reduced Bit Rate (1.62 Gbit/s) and High Bit Rate (2.7 Gbit/s)
Supports 1 Mbit/s AUX channel
Supports Native AUX and I2C-over-AUX transactions
Supports down spreading to minimize EMI
Integrated 50 termination resistors provide impedance matching on both Main Link
lanes and AUX channel
High performance Auto Receive Equalization enabling optimal channel compensation,
device placement flexibility and power saving at CPU/GPU
Supports eDP authentication options: Alternate Scrambler Seed Reset (ASSR) and
Alternate Framing
Supports Full Link training
Supports DisplayPort symbol error rate measurements
Supports PCB routing flexibility by programming for:
AUX P/N swapping
DP Main Link P/N swapping
2.3 LVDS transmitter features
Compatible with ANSI/TIA/EIA-644-A-2001 standard
Supports RGB data packing as per JEIDA and VESA data formats
Supports pixel clock frequency from 6 MHz to 112 MHz
Supports single LVDS bus operation up to 112 mega pixels per second
Supports dual LVDS bus operation up to 224 mega pixels per second
Supports color depth options: 18 bpp, 24 bpp
Programmable center spreading of pixel clock frequency to minimize EMI
Supports 1920 1200 at 60 Hz resolution in dual LVDS bus mode
Programmable LVDS signal swing to pre-compensate for channel attenuation or allow
for power saving
Supports PCB routing flexibility by programming for:
LVDS bus swapping
Channel swapping
Differential signal pair swapping
Supports Data Enable polarity programming
DDC control for EDID ROM access; I2C-bus interface up to 400 kbit/s
2.4 Control and system features
Device programmability
Multi-level configuration pins enabling wider choice
PTN3460I
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 16 August 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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