NXP Semiconductors Electronic Components Datasheet

PTN3460I Datasheet

eDP to LVDS bridge

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PTN3460I

eDP to LVDS bridge for industrial and embedded applications

Rev. 2.1 — 16 August 2016

Product data sheet

1. General description

PTN3460I is an (embedded) DisplayPort to LVDS bridge device that enables connectivity

between an (embedded) DisplayPort (eDP) source and LVDS display panel. It processes

the incoming DisplayPort (DP) stream, performs DP to LVDS protocol conversion and

transmits processed stream in LVDS format.

PTN3460I has two high-speed ports: Receive port facing DP Source (for example,

CPU/GPU/chip set), Transmit port facing the LVDS receiver (for example, LVDS display

panel controller). The PTN3460I can receive DP stream at link rate 1.62 Gbit/s or

2.7 Gbit/s and it can support 1-lane or 2-lane DP operation. It interacts with DP source via

DP Auxiliary (AUX) channel transactions for DP link training and setup.

It supports single bus or dual bus LVDS signaling with color depths of 18 bits per pixel or

24 bits per pixel and pixel clock frequency up to 112 MHz. The LVDS data packing can be

done either in VESA or JEIDA format. Also, the DP AUX interface transports

I2C-over-AUX commands and support EDID-DDC communication with LVDS panel. To

support panels without EDID ROM, the PTN3460I can emulate EDID ROM behavior

avoiding specific changes in system video BIOS.

PTN3460I is suitable for industrial design due to its wide temperature range of 40 C to

+85 C.

PTN3460I provides high flexibility to optimally fit under different platform environments. It

supports three configuration options: multi-level configuration pins, DP AUX interface, and

I2C-bus interface.

PTN3460I can be powered by either 3.3 V supply only or dual supplies (3.3 V/1.8 V) and

is available in the HVQFN56 7 mm  7 mm package with 0.4 mm pitch.

2. Features and benefits

2.1 Device features

 Embedded microcontroller and on-chip Non-Volatile Memory (NVM) allow for flexibility

in firmware updates

 LVDS panel power-up (/down) sequencing control

 Firmware controlled panel power-up (/down) sequence timing parameters

 No external timing reference needed

 EDID ROM emulation to support panels with no EDID ROM. Emulation ON/OFF is set

via configuration pin CFG4 (see Table 14 for more details)

 Supports EDID structure v1.3

 On-chip EDID emulation up to seven different EDID data structures

NXP Semiconductors Electronic Components Datasheet

PTN3460I Datasheet

eDP to LVDS bridge

No Preview Available !

NXP Semiconductors

PTN3460I

eDP to LVDS bridge for industrial and embedded applications

 eDP complying PWM signal generation or PWM signal pass through from eDP source

2.2 DisplayPort receiver features

 Compliant to DP v1.2a and v1.1a

 Compliant to eDP v1.2 and v1.1

 Supports Main Link operation with one or two lanes (select through configuration pin

CFG3, see Table 4 for more details)

 Supports Main Link rate: Reduced Bit Rate (1.62 Gbit/s) and High Bit Rate (2.7 Gbit/s)

 Supports 1 Mbit/s AUX channel

 Supports Native AUX and I2C-over-AUX transactions

 Supports down spreading to minimize EMI

 Integrated 50  termination resistors provide impedance matching on both Main Link

lanes and AUX channel

 High performance Auto Receive Equalization enabling optimal channel compensation,

device placement flexibility and power saving at CPU/GPU

 Supports eDP authentication options: Alternate Scrambler Seed Reset (ASSR) and

Alternate Framing

 Supports Full Link training

 Supports DisplayPort symbol error rate measurements

 Supports PCB routing flexibility by programming for:

 AUX P/N swapping

 DP Main Link P/N swapping

2.3 LVDS transmitter features

 Compatible with ANSI/TIA/EIA-644-A-2001 standard

 Supports RGB data packing as per JEIDA and VESA data formats

 Supports pixel clock frequency from 6 MHz to 112 MHz

 Supports single LVDS bus operation up to 112 mega pixels per second

 Supports dual LVDS bus operation up to 224 mega pixels per second

 Supports color depth options: 18 bpp, 24 bpp

 Programmable center spreading of pixel clock frequency to minimize EMI

 Supports 1920  1200 at 60 Hz resolution in dual LVDS bus mode

 Programmable LVDS signal swing to pre-compensate for channel attenuation or allow

for power saving

 Supports PCB routing flexibility by programming for:

 LVDS bus swapping

 Channel swapping

 Differential signal pair swapping

 Supports Data Enable polarity programming

 DDC control for EDID ROM access; I2C-bus interface up to 400 kbit/s

2.4 Control and system features

 Device programmability

 Multi-level configuration pins enabling wider choice

PTN3460I

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 2.1 — 16 August 2016

2 of 42

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PTN3460I Datasheet

eDP to LVDS bridge

PTN3460I Datasheet

eDP to LVDS bridge

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