PTN2111BD Datasheet | NXP Semiconductors

INTEGRATED CIRCUITS PTN2111 1:10 LVDS clock distribution device Product Data 2001 Jun 19 Philips Semiconductors Philips Semiconductors Product Data 1:10 LVDS clock distribution device PTN2111 Features - 100 ps part-to-part skew - 35 ps output-to-output skew - Differential design - Meets LVDS specification for driver outputs and receiver inputs - Reference voltage available output VBB - Low voltage VCC range of +2.375 V to 2.625 V - High signalling rate capability (above 622 MHz) - Supports open, short, and terminated input fail-safe (HIGH output state) PIN CONFIGURATION 25 GND 24 Q3 23 Q3 22 Q4 21 Q4 20 Q5 19 Q5 18 Q6 17 Q6 Q9 10 Q8 12 Q8 13 Q7 14 Q7 15 GND 9 V CC 16 Q9 11 32 V CC 31 Q0 30 Q0 29 Q1 28 Q1 27 Q2 26 Q2 CK SI CLK0 CLK0 VBB CLK1 CLK1 EN 1 2 3 4 5 6 7 8 - Programmable drivers power off control - Available in LQFP32 package DESCRIPTION The PTN2111 is a low skew programmable 1:10 LVDS clock distribution device. The selected input signal is fanned out to 10 identical differential outputs. The PTN2111 Features an 11-bit Shift Register with a serial-in and a Control Register. The purpose of the Control Register is to enable or power off each output clock channel and to select the clock input. The PTN2111 is specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate-to-gate skew within a device. The final result is a dependable guaranteed low skew device. The PTN2111 can be used for high performance clock distribution in +2.5 V systems with LVDS levels. Designers can take advantage of the device’s performance to distribute low skew clocks across the backplane or the board. ST00013 PIN DESCRIPTION PIN NUMBER 1 2 3 4 5 6 7 8 9, 25 16, 32 31, 29, 27, 24, 22, 20, 18, 15, 13, 11 30, 28, 26, 23, 21, 19, 17, 14, 12, 10 SYMBOL CK SI CLK0 CLK0 VBB CLK1 CLK1 EN GND VCC Q[0:9] NAME AND FUNCTION Control register clock Control register serial-in/CLK_SEL Differential input Differential input...