PLC18V8Z Datasheet | NXP Semiconductors

DESCRIPTION The PLC18V8Z is a universal PAL® device featuring high performance and virtually zero-standby power for power sensitive applications. They are reliable, user-configurable substitutes for discrete TTL/CMOS logic. While patible with TTL and HCT logic, the PLC18V8Z can also replace HC logic over the VCC range of 4.5 to 5.5V. The PLC18V8Z is a two-level logic element prised of 10 inputs, 74 AND gates (product terms) and 8 output Macro cells. Each output features an “Output Macro Cell” which can be individually configured as a dedicated input, a binatorial output, or a registered output with internal feedback. As a result, the PLC18V8Z is capable of emulating all mon 20-pin PAL devices to reduce documentation, inventory, and manufacturing costs. A power-up reset function and a Register Preload function have been incorporated in the PLC18V8Z architecture to facilitate state machine design and testing. With a standby current of less than 100µA and active power consumption of 1.5m A/MHz, the PLC18V8Z is ideally suited for power sensitive applications in battery operated/backed portable instruments and puters. The PLC18V8Z is also processed to industrial requirements for operation over an extended temperature range of -40°C to +85°C and supply voltage of 4.5V to 5.5V. Ordering information can be found on the following page. D, DB, DH, N, Packages I0/CLK I1 I2 I3 I4 I5 I6 I7 I8 1 2 3 4 5 6 7 8 9 20 VCC 19 F7 18 F6 17 F5 16 F4 15 F3 14 F2 13 F1 12 F0 11 I9/OE GND 10 D = Plasitc Small Outline Large Package (300mil-wide) DB = Plastic Shrink Small Outline Package (5.3mm wide) DH = Plastic Thin Shrink Small Outline Package (4.4mm wide) N = Plastic Dual In-Line Package (DIP) (300mil-wide) A Package I2 I0/ I1 CLK VCC F7 2 1 20 19 18 F6 17 F5 16 F4 15 F3 14 F2 9 10 11 12 13 FEATURES 3 I3 I4 I5 I6 I7 4 5 6 7 8 - 20-pin Universal Programmable Array Logic - Virtually Zero-Standby-power - 20µA (typical) - Available in DIP, PLCC, SOL (Small Outline), SSOP (Shrink...