Philips Semiconductors
PowerMOS transistor
Isolated version of PHP8N50E
Objective specification
PHX5N50E
GENERAL DESCRIPTION
N-channel enhancement mode
field-effect power transistor in a full
pack, plastic envelope featuring high
avalanche energy capability, stable
blocking voltage, fast switching and
high thermal cycling performance
with low thermal resistance. Intended
for use in Switched Mode Power
Supplies (SMPS), motor control
circuits and general purpose
switching applications.
QUICK REFERENCE DATA
SYMBOL PARAMETER
VDS
ID
Ptot
RDS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state resistance
MAX.
500
4
30
0.8
UNIT
V
A
W
Ω
PINNING - SOT186A
PIN DESCRIPTION
1 gate
2 drain
3 source
case isolated
PIN CONFIGURATION
case
12 3
SYMBOL
d
g
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDS
VDGR
±VGS
ID
IDM
IDR
IDRM
Ptot
Tstg
Tj
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (pulse peak
value)
Source-drain diode current
(DC)
Source-drain diode current
(pulse peak value)
Total power dissipation
Storage temperature
Junction temperature
RGS = 20 kΩ
Ths = 25 ˚C
Ths = 100 ˚C
Ths = 25 ˚C
Ths = 25 ˚C
Ths = 25 ˚C
Ths = 25 ˚C
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
WDSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
WDSR1
Drain-source repetitive
unclamped inductive turn-off
energy
CONDITIONS
ID = 8 A; VDD ≤ 50 V; VGS = 10 V;
RGS = 50 Ω
Tj = 25˚C prior to surge
Tj = 100˚C prior to surge
ID = 8 A; VDD ≤ 50 V; VGS = 10 V;
RGS = 50 Ω; Tj ≤ 150 ˚C
MIN.
-
-
-
-
-
-
-
-
-
-55
-
MIN.
-
-
-
MAX.
500
500
30
4
2.5
16
4
16
30
150
150
MAX.
510
82
13
UNIT
V
V
V
A
A
A
A
A
W
˚C
˚C
UNIT
mJ
mJ
mJ
1. Pulse width and frequency limited by Tj(max)
November 1996
1
Rev 1.000
