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PHU2N50E Datasheet

PowerMOS transistors Avalanche energy rated

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Philips Semiconductors
PowerMOS transistors
Avalanche energy rated
Product specification
PHU2N50E
FEATURES
• Repetitive Avalanche Rated
• Fast switching
• Stable off-state characteristics
• High thermal cycling performance
• Low thermal resistance
• Extremely high dV/dt capability
QUICK REFERENCE DATA
VDSS = 500 V
ID = 2 A
RDS(ON) 5
GENERAL DESCRIPTION
N-channel, enhancement mode field-effect power transistor, intended for use in Compact Fluorescent Lamps (CFL)
and low power ballasts. The PHU2N50E is compatible with self oscillating and IC driven circuits, including the UBA2021
ballast controller IC. Other applications include off line switched mode power supplies and D.C. to D.C. converters.
The PHU2N50E is supplied in the SOT533 (I-PAK) leaded package.
PINNING
SYMBOL
SOT533
PIN DESCRIPTION
------------- ---------------------------------
1 gate
d
2 drain
3 source
g
tab drain
123
s Top view
MBK915
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDSS
VDGR
VGS
ID
IDM
PD
dV/dt
Tj, Tstg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total dissipation
Peak Diode Recovery
voltage slope. (See fig. 19)
Operating junction and
storage temperature range
Tj = 25 ˚C to 150˚C
Tj = 25 ˚C to 150˚C; RGS = 20 k
Tmb = 25 ˚C; VGS = 10 V
Tmb = 100 ˚C; VGS = 10 V
Tmb = 25 ˚C
Tmb = 25 ˚C
Ids 2.0 A; dI/dt = 100 A/µs;
Vs = 8V; Tj < Tjmax
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
500
500
± 30
2
1.3
8
50
5.2
150
UNIT
V
V
V
A
A
A
W
V/ns
˚C
May 1999 1 Rev 1.000


NXP Semiconductors Electronic Components Datasheet

PHU2N50E Datasheet

PowerMOS transistors Avalanche energy rated

No Preview Available !

Philips Semiconductors
PowerMOS transistors
Avalanche energy rated
Product specification
PHU2N50E
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
EAS
EAR
IAS, IAR
Non-repetitive avalanche
energy
Unclamped inductive load, IAS = 1.26 A;
tp = 0.2 ms; Tj prior to avalanche = 25˚C;
VDD 50 V; RGS = 50 ; VGS = 10 V; refer
to fig:17
Repetitive avalanche energy1 IAR = 2 A; tp = 2.5 µs; Tj prior to
avalanche = 25˚C; RGS = 50 ; VGS = 10 V;
refer to fig:18
Repetitive and non-repetitive
avalanche current
MIN.
-
-
-
MAX.
82
3.3
2
UNIT
mJ
mJ
A
THERMAL RESISTANCES
SYMBOL PARAMETER
Rth j-mb
Rth j-a
Thermal resistance junction
to mounting base
Thermal resistance junction
to ambient
CONDITIONS
In free air
MIN. TYP. MAX. UNIT
- - 2.5 K/W
- 70 - K/W
ELECTRICAL CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
V(BR)DSS Drain-source breakdown
voltage
VGS = 0 V; ID = 0.25 mA
V(BR)DSS / Drain-source breakdown
Tj voltage temperature
coefficient
VDS = VGS; ID = 0.25 mA
RDS(ON)
VGS(TO)
gfs
IDSS
IGSS
Drain-source on resistance VGS = 10 V; ID = 1 A
Gate threshold voltage
VDS = VGS; ID = 0.25 mA
Forward transconductance VDS = 30 V; ID = 1 A
Drain-source leakage current VDS = 500 V; VGS = 0 V
VDS = 500 V; VGS = 0 V; Tj = 125 ˚C
Gate-source leakage current VGS = ±30 V; VDS = 0 V
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 2 A; VDD = 400 V; VGS = 10 V
td(on) Turn-on delay time
tr Turn-on rise time
td(off) Turn-off delay time
tf Turn-off fall time
VDD = 250 V; RD = 120 ;
RG = 24
Ld Internal drain inductance Measured from tab to centre of die
Ls Internal source inductance Measured from source lead to source
bond pad
Ciss Input capacitance
Coss Output capacitance
Crss Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
MIN. TYP. MAX. UNIT
500 -
-V
- 0.1 - %/K
- 3.1 5
2.0 3.0 4.0 V
0.5 1.3 -
S
- 1 25 µA
- 77 250 µA
- 10 200 nA
- 20 25 nC
- 2 3 nC
- 12 15 nC
- 10 - ns
- 20 - ns
- 60 - ns
- 20 - ns
- 3.5 - nH
- 7.5 - nH
- 236 -
- 40 -
- 22 -
pF
pF
pF
1 pulse width and repetition rate limited by Tj max.
May 1999
2
Rev 1.000


Part Number PHU2N50E
Description PowerMOS transistors Avalanche energy rated
Maker NXP
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