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NXP Semiconductors Electronic Components Datasheet

PHP87N03LT Datasheet

N-channel TrenchMOS transistor Logic level FET

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Philips Semiconductors
N-channel TrenchMOStransistor
Logic level FET
Product specification
PHP87N03LT, PHB87N03LT
PHD87N03LT
FEATURES
’Trench’ technology
• Very low on-state resistance
• Fast switching
• Low thermal resistance
• Logic level compatible
SYMBOL
d
g
s
QUICK REFERENCE DATA
VDSS = 25 V
ID = 75 A
RDS(ON) 9.5 m(VGS = 10 V)
RDS(ON) 10.5 m(VGS = 5 V)
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology.
Applications:-
• High frequency computer motherboard d.c. to d.c. converters
• High current switching
The PHP87N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB87N03LT is supplied in the SOT404 (D2PAK) surface mounting package.
The PHD87N03LT is supplied in the SOT428 (DPAK)surface mounting package.
PINNING
SOT78 (TO220AB) SOT404 (D2PAK)
PIN DESCRIPTION
1 gate
tab
tab
SOT428 (DPAK)
tab
2 drain 1
3 source
tab drain
1 23
2
13
2
13
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDSS
VDGR
VGS
VGSM
ID
IDM
Ptot
Tj, Tstg
Drain-source voltage
Drain-gate voltage
Gate-source voltage (DC)
Gate-source voltage (pulse
peak value)
Drain current (DC)
Drain current (pulse peak
value)
Total power dissipation
Operating junction and
storage temperature
Tj = 25 ˚C to 175˚C
Tj = 25 ˚C to 175˚C; RGS = 20 k
Tj 150 ˚C
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
25
25
± 15
± 20
75
61
240
142
175
UNIT
V
V
V
V
A
A
A
W
˚C
1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.
October 1999
1
Rev 1.600


NXP Semiconductors Electronic Components Datasheet

PHP87N03LT Datasheet

N-channel TrenchMOS transistor Logic level FET

No Preview Available !

Philips Semiconductors
N-channel TrenchMOStransistor
Logic level FET
Product specification
PHP87N03LT, PHB87N03LT
PHD87N03LT
THERMAL RESISTANCES
SYMBOL PARAMETER
Rth j-mb
Rth j-a
Thermal resistance junction
to mounting base
Thermal resistance junction
to ambient
CONDITIONS
SOT78 package, in free air
SOT404 or SOT428 package, pcb
mounted, minimum footprint
MIN. TYP. MAX. UNIT
- - 1.05 K/W
- 60 - K/W
- 50 - K/W
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
WDSS
Drain-source non-repetitive ID = 45 A; VDD 15 V;
unclamped inductive turn-off VGS = 5 V; RGS = 50 ; Tmb = 25 ˚C
energy
MIN.
-
MAX.
200
UNIT
mJ
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
V(BR)DSS
VGS(TO)
RDS(ON)
gfs
IGSS
IDSS
Qg(tot)
Qgs
Qgd
td on
tr
td off
tf
Ld
Ld
Ls
Drain-source breakdown
voltage
Gate threshold voltage
Drain-source on-state
resistance
Forward transconductance
Gate source leakage current
Zero gate voltage drain
current
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
VGS = 0 V; ID = 0.25 mA;
Tj = -55˚C
VDS = VGS; ID = 1 mA
Tj = 175˚C
Tj = -55˚C
VGS = 5 V; ID = 25 A
VGS = 10 V; ID = 25 A
VGS = 5 V; ID = 25 A; Tj = 175˚C
VDS = 25 V; ID = 25 A
VGS = ±5 V; VDS = 0 V
VDS = 25 V; VGS = 0 V;
Tj = 175˚C
ID = 75 A; VDD = 15 V; VGS = 5 V
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 15 V; ID = 25 A;
VGS = 10 V; RG = 5
Resistive load
Internal drain inductance
Internal drain inductance
Internal source inductance
Measured tab to centre of die
Measured from drain lead to centre of die
(SOT78 package only)
Measured from source lead to source
bond pad
Ciss Input capacitance
Coss Output capacitance
Crss Feedback capacitance
VGS = 0 V; VDS = 20 V; f = 1 MHz
MIN. TYP. MAX. UNIT
25 -
-V
22 -
-V
1 1.5 2
V
0.5 -
-V
- - 2.3 V
- 9 10.5 m
- 8.5 9.5 m
- - 19.5 m
12 51 - S
- 10 100 nA
- 0.05 10 µA
- - 500 µA
- 39 -
-9-
- 18.5 -
nC
nC
nC
- 9 15 ns
- 54 70 ns
- 136 160 ns
- 85 100 ns
- 3.5 - nH
- 4.5 - nH
- 7.5 - nH
- 2304 -
- 620 -
- 448 -
pF
pF
pF
October 1999
2
Rev 1.600


Part Number PHP87N03LT
Description N-channel TrenchMOS transistor Logic level FET
Maker NXP
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