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NXP Semiconductors Electronic Components Datasheet

PHP65N06LT Datasheet

TrenchMOS transistor Logic level FET

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Philips Semiconductors
TrenchMOStransistor
Logic level FET
Product specification
PHP65N06LT, PHB65N06LT
FEATURES
’Trench’ technology
• Very low on-state resistance
• Fast switching
• Stable off-state characteristics
• High thermal cycling performance
• Low thermal resistance
SYMBOL
g
d
s
QUICK REFERENCE DATA
VDSS = 55 V
ID = 63 A
RDS(ON) 18 m(VGS = 5 V)
RDS(ON) 16 m(VGS = 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology.
The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching
applications.
The PHP65N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB65N06LT is supplied in the SOT404 surface mounting package.
PINNING
PIN DESCRIPTION
1 gate
SOT78 (TO220AB)
tab
SOT404
tab
2 drain1
3 source
tab drain
1 23
2
13
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDSS
VDGR
VGS
ID
IDM
PD
Tj, Tstg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
Tj = 25 ˚C to 175˚C
Tj = 25 ˚C to 175˚C; RGS = 20 k
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
55
55
± 13
63
44
240
150
175
UNIT
V
V
V
A
A
A
W
˚C
1 It is not possible to make connection to pin 2 of the SOT404 package.
January 1998
1
Rev 1.300


NXP Semiconductors Electronic Components Datasheet

PHP65N06LT Datasheet

TrenchMOS transistor Logic level FET

No Preview Available !

Philips Semiconductors
TrenchMOStransistor
Logic level FET
Product specification
PHP65N06LT, PHB65N06LT
THERMAL RESISTANCES
SYMBOL PARAMETER
Rth j-mb
Rth j-a
Thermal resistance junction
to mounting base
Thermal resistance junction
to ambient
CONDITIONS
SOT78 package, in free air
SOT404 package, pcb mounted, minimum
footprint
TYP.
-
60
50
MAX.
1.0
-
-
UNIT
K/W
K/W
K/W
ESD LIMITING VALUE
SYMBOL PARAMETER
VC Electrostatic discharge
capacitor voltage, all pins
CONDITIONS
Human body model (100 pF, 1.5 k)
MIN.
-
MAX.
2
UNIT
kV
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
V(BR)DSS
V(BR)GSS
VGS(TO)
RDS(ON)
gfs
IGSS
IDSS
Qg(tot)
Qgs
Qgd
td on
tr
td off
tf
Ld
Ld
Ls
Drain-source breakdown
voltage
Gate-source breakdown
voltage
Gate threshold voltage
Drain-source on-state
resistance
Forward transconductance
Gate source leakage current
Zero gate voltage drain
current
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
VGS = 0 V; ID = 0.25 mA;
IG = ±1 mA;
Tj = -55˚C
VDS = VGS; ID = 1 mA
VGS = 5 V; ID = 25 A
VGS = 10 V; ID = 25 A
VDS = 25 V; ID = 25 A
VGS = ±5 V; VDS = 0 V
VDS = 55 V; VGS = 0 V;
Tj = 175˚C
Tj = -55˚C
Tj = 175˚C
Tj = 175˚C
Tj = 175˚C
ID = 50 A; VDD = 44 V; VGS = 5 V
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; ID = 25 A;
VGS = 5 V; RG = 10
Resistive load
Internal drain inductance
Internal drain inductance
Internal source inductance
Measured from tab to centre of die
Measured from drain lead to centre of die
(SOT78 package only)
Measured from source lead to source
bond pad
Ciss Input capacitance
Coss Output capacitance
Crss Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
MIN. TYP. MAX. UNIT
55 -
50 -
10 -
-V
-V
-V
1.0 1.5 2.0 V
0.5 -
-V
- - 2.3 V
- 15 18 m
- 13 16 m
- - 38 m
25 52 - S
- 0.02 1 µA
- - 20 µA
- 0.05 10 µA
- - 500 µA
- 34 - nC
- 8 - nC
- 17 - nC
- 30 45 ns
- 80 130 ns
- 100 140 ns
- 50 75 ns
- 3.5 - nH
- 4.5 - nH
- 7.5 - nH
- 2000 2600 pF
- 390 490 pF
- 200 290 pF
January 1998
2
Rev 1.300


Part Number PHP65N06LT
Description TrenchMOS transistor Logic level FET
Maker NXP
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