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NXP Semiconductors Electronic Components Datasheet

PHP55N03LTA Datasheet

N-channel enhancement mode field-effect transistor

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PHP55N03LTA;PHB55N03LTA;
PHD55N03LTA
N-channel enhancement mode field-effect transistor
Rev. 02 — 2 August 2001
Product data
1. Description
N-channel logic level field-effect power transistor in a plastic package using
TrenchMOS™1 technology.
Product availability:
PHP55N03LTA in a SOT78 (TO-220AB)
PHB55N03LTA in a SOT404 (D2-PAK)
PHD55N03LTA in a SOT428 (D-PAK).
2. Features
s Low on-state resistance
s Fast switching.
3. Applications
s Computer motherboard high frequency DC to DC converters.
4. Pinning information
Table 1: Pinning - SOT78, SOT404, SOT428 simplified outline and symbol
Pin Description
Simplified outline
1 gate (g)
2 drain (d)
mb
[1]
mb
mb
3 source (s)
mb mounting base,
connected to drain (d)
MBK106
123
SOT78 (TO-220AB)
2
1 3 MBK116
SOT404 (D2-PAK)
2
1
Top view
3
MBK091
SOT428 (D-PAK)
Symbol
g
MBB076
d
s
[1] It is not possible to make connection to pin 2 of the SOT404 and SOT428 packages.
1. TrenchMOS is a trademark of Royal Phillips Electronics.


NXP Semiconductors Electronic Components Datasheet

PHP55N03LTA Datasheet

N-channel enhancement mode field-effect transistor

No Preview Available !

Philips Semiconductors
PHP55N03LTA series
N-channel enhancement mode field-effect transistor
5. Quick reference data
Table 2: Quick reference data
Symbol Parameter
VDS
ID
Ptot
Tj
RDSon
drain-source voltage (DC)
drain current (DC)
total power dissipation
junction temperature
drain-source on-state resistance
6. Limiting values
Conditions
Tj = 25 to 175 °C
Tmb = 25 °C; VGS = 5 V
Tmb = 25 °C
VGS = 10 V; ID = 25 A; Tj = 25 °C
VGS = 5 V; ID = 25 A; Tj = 25 °C
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
VDS
VDGR
VGS
VGSM
drain-source voltage (DC)
drain-gate voltage (DC)
gate-source voltage (DC)
gate-source voltage
ID drain current (DC)
IDM peak drain current
Ptot total power dissipation
Tstg storage temperature
Tj operating junction temperature
Source-drain diode
Tj = 25 to 175 °C
Tj = 25 to 175 °C; RGS = 20 k
tp 50 µs pulsed;
duty cycle 25%; Tj 150 °C
Tmb = 25 °C; VGS = 5 V; Figure 2 and 3
Tmb = 100 °C; VGS = 5 V; Figure 2
Tmb = 25 °C; pulsed; tp 10 µs; Figure 3
Tmb = 25 °C; Figure 1
IS source (diode forward) current (DC) Tmb = 25 °C
ISM peak source (diode forward) current Tmb = 25 °C; pulsed; tp 10 µs
Avalanche ruggedness
EAS
non-repetitive avalanche energy
unclamped inductive load; ID = 55 A;
tp = 0.1 ms; VDD = 15 V; RGS = 50 ;
VGS = 5V; starting Tj = 25 °C
IAS non-repetitive avalanche current unclamped inductive load; VDD = 15 V;
RGS = 50 ; VGS = 5 V; starting Tj = 25 °C
Typ Max Unit
- 25 V
- 55 A
- 85 W
- 175 °C
11 14 m
15 18 m
Min Max Unit
- 25 V
- 25 V
- ±15 V
- ±20 V
- 55 A
- 38 A
- 220 A
- 85 W
55 +175 °C
55 +175 °C
- 55 A
- 220 A
- 60 mJ
- 55 A
9397 750 08642
Product data
Rev. 02 — 2 August 2001
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
2 of 14


Part Number PHP55N03LTA
Description N-channel enhancement mode field-effect transistor
Maker NXP
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PHP55N03LTA Datasheet PDF






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