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PHP21N06LT Datasheet

N-channel TrenchMOS transistor Logic level FET

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Philips Semiconductors
N-channel TrenchMOStransistor
Logic level FET
Product specification
PHP21N06LT, PHB21N06LT
PHD21N06LT
FEATURES
’Trench’ technology
• Low on-state resistance
• Fast switching
• Logic level compatible
SYMBOL
d
g
s
QUICK REFERENCE DATA
VDSS = 55 V
ID = 19 A
RDS(ON) 75 m(VGS = 5 V)
RDS(ON) 70 m(VGS = 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology.
Applications:-
• d.c. to d.c. converters
• switched mode power supplies
The PHP21N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB21N06LT is supplied in the SOT404 (D2PAK) surface mounting package.
The PHD21N06LT is supplied in the SOT428 (DPAK) surface mounting package.
PINNING
SOT78 (TO220AB) SOT404 (D2PAK)
PIN DESCRIPTION
1 gate
tab
tab
SOT428 (DPAK)
tab
2 drain 1
3 source
tab drain
1 23
2
13
2
13
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDSS
VDGR
VGS
VGSM
ID
IDM
PD
Tj, Tstg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Pulsed gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
Tj = 25 ˚C to 175˚C
Tj = 25 ˚C to 175˚C; RGS = 20 k
Tj 150˚C
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
55
55
± 15
± 20
19
13
76
56
175
UNIT
V
V
V
V
A
A
A
W
˚C
1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.
August 1999
1
Rev 1.500


NXP Semiconductors Electronic Components Datasheet

PHP21N06LT Datasheet

N-channel TrenchMOS transistor Logic level FET

No Preview Available !

Philips Semiconductors
N-channel TrenchMOStransistor
Logic level FET
Product specification
PHP21N06LT, PHB21N06LT
PHD21N06LT
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
EAS Non-repetitive avalanche Unclamped inductive load, IAS = 9.7 A;
energy
tp = 100 µs; Tj prior to avalanche = 25˚C;
VDD 25 V; RGS = 50 ; VGS = 5 V; refer to
fig:15
IAS Peak non-repetitive
avalanche current
MIN.
-
-
MAX.
34
19
UNIT
mJ
A
THERMAL RESISTANCES
SYMBOL PARAMETER
Rth j-mb
Rth j-a
Thermal resistance junction
to mounting base
Thermal resistance junction
to ambient
CONDITIONS
SOT78 package, in free air
SOT428 and SOT404 package, pcb
mounted, minimum footprint
TYP.
-
60
50
MAX.
2.7
-
-
UNIT
K/W
K/W
K/W
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
V(BR)DSS
VGS(TO)
RDS(ON)
gfs
IGSS
IDSS
Qg(tot)
Qgs
Qgd
td on
tr
td off
tf
Ld
Ld
Ls
Drain-source breakdown
voltage
Gate threshold voltage
Drain-source on-state
resistance
Forward transconductance
Gate source leakage current
Zero gate voltage drain
current
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
VGS = 0 V; ID = 0.25 mA;
VDS = VGS; ID = 1 mA
VGS = 10 V; ID = 10 A
VGS = 5 V; ID = 10 A
VDS = 25 V; ID = 10 A
VGS = ±5 V; VDS = 0 V
VDS = 55 V; VGS = 0 V;
Tj = -55˚C
Tj = 175˚C
Tj = -55˚C
Tj = 175˚C
Tj = 175˚C
ID = 20 A; VDD = 44 V; VGS = 5 V
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; RD = 1.2 ;
RG = 10 ; VGS = 5 V
Resistive load
Internal drain inductance
Internal drain inductance
Internal source inductance
Measured from tab to centre of die
Measured from drain lead to centre of die
(SOT78 package only)
Measured from source lead to source
bond pad
Ciss Input capacitance
Coss Output capacitance
Crss Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
MIN. TYP. MAX. UNIT
55 -
-V
50 -
-V
1.0 1.5 2.0 V
0.5 -
-V
- - 2.3 V
- 55 70 m
- 60 75 m
- - 158 m
5 13 - S
- 10 100 nA
- 0.05 10 µA
- - 500 µA
- 9.4 - nC
- 2.2 - nC
- 5.4 - nC
- 7 15 ns
- 88 120 ns
- 25 40 ns
- 25 45 ns
- 3.5 - nH
- 4.5 - nH
- 7.5 - nH
- 466 650 pF
- 95 135 pF
- 71 85 pF
August 1999
2
Rev 1.500


Part Number PHP21N06LT
Description N-channel TrenchMOS transistor Logic level FET
Maker NXP
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