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PHD108NQ03LT Datasheet

N-channel TrenchMOS logic level FET

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PHD108NQ03LT
N-channel TrenchMOS logic level FET
Rev. 04 — 5 June 2009
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
„ Low conduction losses due to low
on-state resistance
„ Simple gate drive required due to low
gate charge
„ Suitable for logic level gate drive
sources
1.3 Applications
„ DC-to-DC convertors
„ Switched-mode power supplies
1.4 Quick reference data
Table 1. Quick reference
Symbol Parameter
Conditions
VDS drain-source voltage Tj 25 °C; Tj 175 °C
ID drain current
Tmb = 25 °C; VGS = 5 V; see
Figure 1; see Figure 3
Ptot total power
dissipation
Tmb = 25 °C; see Figure 2
Avalance ruggedness
EDS(AL)S non-repetitive
drain-source
avalanche energy
Dynamic characteristics
VGS = 10 V; Tj(init) = 25 °C;
ID = 43 A; Vsup 25 V;
unclamped; tp = 0.25 ms;
RGS = 50
QGD
gate-drain charge VGS = 4.5 V; ID = 25 A;
VDS = 12 V; Tj = 25 °C; see
Figure 12; see Figure 13
Static characteristics
RDSon
drain-source
on-state resistance
VGS = 10 V; ID = 25 A;
Tj = 25 °C; see Figure 10;
see Figure 11
Min Typ Max Unit
- - 25 V
- - 75 A
- - 187 W
- - 180 mJ
- 5.6 - nC
-
5.3 6
m


NXP Semiconductors Electronic Components Datasheet

PHD108NQ03LT Datasheet

N-channel TrenchMOS logic level FET

No Preview Available !

NXP Semiconductors
PHD108NQ03LT
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2. Pinning information
Pin Symbol Description
1G
gate
2D
drain
3S
source
mb D
mounting base; connected to
drain
[1] It is not possible to make a connection to pin 2.
Simplified outline
mb
[1]
2
13
SOT428
(SC-63; DPAK)
3. Ordering information
Graphic symbol
D
G
mbb076 S
Table 3. Ordering information
Type number
Package
Name
Description
PHD108NQ03LT SC-63;
DPAK
plastic single-ended surface-mounted package (DPAK); 3 leads (one
lead cropped)
4. Limiting values
Version
SOT428
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDS
VDGR
VGS
ID
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
IDM peak drain current
Ptot total power dissipation
Tstg storage temperature
Tj junction temperature
Source-drain diode
Conditions
Tj 25 °C; Tj 175 °C
Tj 25 °C; Tj 175 °C; RGS = 20 k
VGS = 5 V; Tmb = 25 °C; see Figure 1; see Figure 3
VGS = 5 V; Tmb = 100 °C; see Figure 1
tp 10 µs; pulsed; Tmb = 25 °C; see Figure 3
Tmb = 25 °C; see Figure 2
IS source current Tmb = 25 °C
ISM peak source current tp 10 µs; pulsed; Tmb = 25 °C
Avalance ruggedness
EDS(AL)S
non-repetitive
VGS = 10 V; Tj(init) = 25 °C; ID = 43 A; Vsup 25 V;
drain-source avalanche unclamped; tp = 0.25 ms; RGS = 50
energy
Min Max Unit
- 25 V
- 25 V
-20 20
V
- 75 A
- 75 A
- 240 A
- 187 W
-55 175 °C
-55 175 °C
- 75 A
- 240 A
- 180 mJ
PHD108NQ03LT_4
Product data sheet
Rev. 04 — 5 June 2009
© NXP B.V. 2009. All rights reserved.
2 of 12


Part Number PHD108NQ03LT
Description N-channel TrenchMOS logic level FET
Maker NXP
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