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NXP Semiconductors Electronic Components Datasheet

PHB12NQ15T Datasheet

N-channel TrenchMOS transistor

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Philips Semiconductors
N-channel TrenchMOStransistor
Product specification
PHP12NQ15T, PHB12NQ15T
PHD12NQ15T
FEATURES
’Trench’ technology
• Low on-state resistance
• Fast switching
• Low thermal resistance
SYMBOL
d
g
s
QUICK REFERENCE DATA
VDSS = 150 V
ID = 12.5 A
RDS(ON) 200 m
GENERAL DESCRIPTION
N-channel enhancement mode field-effect power transistor in a plastic envelope using ’trench’ technology. The device
has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications.
The PHP12NQ15T is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB12NQ15T is supplied in the SOT404 (D2PAK) surface mounting package.
The PHD12NQ15T is supplied in the SOT428 (DPAK) surface mounting package.
PINNING
SOT78 (TO220AB) SOT404 (D2PAK)
SOT428 (DPAK)
PIN DESCRIPTION
tab
tab tab
1 gate
2 drain 1
3 source
tab drain
1 23
2
13
2
13
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDSS
VDGR
VGS
ID
IDM
PD
Tj, Tstg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
Tj = 25 ˚C to 175˚C
Tj = 25 ˚C to 175˚C; RGS = 20 k
Tmb = 25 ˚C; VGS = 10 V
Tmb = 100 ˚C; VGS = 10 V
Tmb = 25 ˚C
Tmb = 25 ˚C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
150
150
± 20
12.5
8.8
50
88
175
UNIT
V
V
V
A
A
A
W
˚C
1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.
August 1999
1
Rev 1.000


NXP Semiconductors Electronic Components Datasheet

PHB12NQ15T Datasheet

N-channel TrenchMOS transistor

No Preview Available !

Philips Semiconductors
N-channel TrenchMOStransistor
Product specification
PHP12NQ15T, PHB12NQ15T
PHD12NQ15T
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
EAS Non-repetitive avalanche Unclamped inductive load, IAS = 9.5 A;
energy
tp = 100 µs; Tj prior to avalanche = 25˚C;
VDD 25 V; RGS = 50 ; VGS = 10 V; refer
to fig:15
IAS Peak non-repetitive
avalanche current
MIN.
-
MAX.
93
UNIT
mJ
- 12.5 A
THERMAL RESISTANCES
SYMBOL PARAMETER
Rth j-mb
Rth j-a
Thermal resistance junction
to mounting base
Thermal resistance junction
to ambient
CONDITIONS
SOT78 package, in free air
SOT404 & SOT428 packages, pcb
mounted, minimum footprint
MIN. TYP. MAX. UNIT
- - 1.7 K/W
- 60 - K/W
- 50 - K/W
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
V(BR)DSS
VGS(TO)
RDS(ON)
IGSS
IDSS
Qg(tot)
Qgs
Qgd
td on
tr
td off
tf
Ld
Ld
Ls
Drain-source breakdown
voltage
Gate threshold voltage
Drain-source on-state
resistance
Gate source leakage current
Zero gate voltage drain
current
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
VGS = 0 V; ID = 0.25 mA;
VDS = VGS; ID = 1 mA
VGS = 10 V; ID = 6 A
VGS = ± 10 V; VDS = 0 V
VDS = 150 V; VGS = 0 V
Tj = -55˚C
Tj = 175˚C
Tj = -55˚C
Tj = 175˚C
Tj = 175˚C
ID = 12 A; VDD = 120 V; VGS = 10 V
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 75 V; RD = 6.8 ;
VGS = 10 V; RG = 5.6
Resistive load
Internal drain inductance
Internal drain inductance
Internal source inductance
Measured tab to centre of die
Measured from drain lead to centre of die
(SOT78 package only)
Measured from source lead to source
bond pad
Ciss Input capacitance
Coss Output capacitance
Crss Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
MIN. TYP. MAX. UNIT
150 -
-V
133 -
-V
234V
1- -V
- 6V
- 180 200 m
- - 560 m
- 10 100 nA
- 0.05 10 µA
- - 500 µA
- 20 - nC
- 4.4 - nC
- 8 - nC
- 8 - ns
- 20 - ns
- 20 - ns
- 12 - ns
- 3.5 - nH
- 4.5 - nH
- 7.5 - nH
- 860 -
- 108 -
- 57 -
pF
pF
pF
August 1999
2
Rev 1.000


Part Number PHB12NQ15T
Description N-channel TrenchMOS transistor
Maker NXP
Total Page 12 Pages
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