100-250 MHz differential 1:10 clock driver
• ESD classification testing is done to JEDEC Standard JESD22.
Protection exceeds 2000 V to HBM per method A114.
• Latch-up testing is done to JEDEC Standard JESD78 which
exceeds 100 mA
• Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications as per JEDEC specifications
• 1-to-10 differential clock distribution
• Very low skew (< 100 ps) and jitter (< 100 ps)
• Operation from 2.2 V to 2.7 V AVDD and 2.3 V to 2.7 V VDD
• SSTL_2 interface clock inputs and outputs
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Full DDR solution provided when used with SSTL16877 or
• Designed for DDR 266, 300, and 333 DIMM applications
• Available in TSSOP-48 and TVSOP-48 packages
The PCKV857A is a high-performance, low-skew, low-jitter zero
delay buffer designed for 2.5 V VDD and 2.5 V AVDD operation and
differential data input and output levels.
The PCKV857A is a zero delay buffer that distributes a differential
clock input pair (CLK, CLK) to ten differential pairs of clock outputs
(Y[0:9], Y[0:9]) and one differential pair feedback clock outputs
(FBOUT, FBOUT) . The clock outputs are controlled by the clock
inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), and the analog
power input (AVDD). When PWRDWN is HIGH, the outputs switch in
phase and frequency with CLK. When PWRDWN is LOW, all
outputs are disabled to HIGH impedance state (3-State), and the
PLL is shut down (LOW power mode). The device also enters the
LOW power mode when the input frequency falls below 20 MHz. An
input frequency detection circuit will detect the LOW frequency
condition and after applying a > 20 MHz input signal, the detection
circuit turns on the PLL again and enables the outputs.
When AVDD is grounded, the PLL is turned off and bypassed for test
purposes. The PCKV857A is also able to track spread spectrum
clocking for reduced EMI.
The PCKV857A is characterized for operation from 0 to +70 °C.
48-Pin Plastic TSSOP
48-Pin Plastic TSSOP (TVSOP)
0 to +70 °C
0 to +70 °C
2003 Jul 31