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PCKV857 Datasheet

70-190 MHz differential 1:10 clock driver

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INTEGRATED CIRCUITS
PCKV857
70–190 MHz differential 1:10 clock driver
Product data
Supersedes data of 2001 Mar 16
File under Intergrated Circuits ICL03
2001 Jun 12
Philips
Semiconductors


NXP Semiconductors Electronic Components Datasheet

PCKV857 Datasheet

70-190 MHz differential 1:10 clock driver

No Preview Available !

Philips Semiconductors
70–190 MHz differential 1:10 clock driver
Product data
PCKV857
FEATURES
ESD classification testing is done to JEDEC Standard JESD22.
Protection exceeds 2000 V to HBM per method A114.
Latch-up testing is done to JEDEC Standard JESD78 which
exceeds 100 mA
Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications as per JEDEC specifications
1-to-10 differential clock distribution
Very low skew (< 100 ps) and jitter (< 100 ps)
Operation from 2.2 V to 2.7 V AVDD and 2.3 V to 2.7 V VDD
SSTL_2 interface clock inputs and outputs
CMOS control signal input
Test mode enables buffers while disabling PLL
Low current power-down mode
Tolerant of Spread Spectrum input clock
Full DDR solution provided when used with SSTL16877 or
SSTV16857
See PCKV856 for I2C capable clock driver
DESCRIPTION
The PCKV857 is a high-performance, low-skew, low-jitter zero delay
buffer designed for 2.5 V VDD and 2.5 V AVDD operation and
differential data input and output levels.
The PCKV857 is a zero delay buffer that distributes a differential
clock input pair (CLK, CLK) to ten differential pairs of clock outputs
(Y[0:9], Y[0:9]) and one differential pair feedback clock outputs
(FBOUT, FBOUT) . The clock outputs are controlled by the clock
inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), and the analog
power input (AVDD). When PWRDWN is high, the outputs switch in
phase and frequency with CLK. When PWRDWN is low, all outputs
are disabled to high impedance state (3-State), and the PLL is shut
down (low power mode). The device also enters the low power
mode when the input frequency falls below 20 MHz. An input
frequency detection circuit will detect the low frequency condition
and after applying a > 20 MHz input signal, the detection circuit
turns on the PLL again and enables the outputs.
When AVDD is grounded, the PLL is turned off and bypassed for test
purposes. The PCKV857 is also able to track spread spectrum
clocking for reduced EMI.
The PCKV857 is characterized for operation from 0 to +70 °C.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
48-Pin Plastic TSSOP
0 to +70 °C
PIN CONFIGURATION
GND 1
Y0 2
Y0 3
VDDQ 4
Y1 5
Y1 6
GND 7
GND 8
Y2 9
Y2 10
VDDQ 11
VDDQ 12
CLK 13
CLK 14
VDDQ 15
AVDD 16
AGND 17
GND 18
Y3 19
Y3 20
VDDQ 21
Y4 22
Y4 23
GND 24
ORDER CODE
PCKV857DGG
48 GND
47 Y5
46 Y5
45 VDDQ
44 Y6
43 Y6
42 GND
41 GND
40 Y7
39 Y7
38 VDDQ
37 PWRDWN
36 FBIN
35 FBIN
34 VDDQ
33 FBOUT
32 FBOUT
31 GND
30 Y8
29 Y8
28 VDDQ
27 Y9
26 Y9
25 GND
SW00691
DRAWING NUMBER
SOT362-1
2001 Jun 12
2 853–2242 26485


Part Number PCKV857
Description 70-190 MHz differential 1:10 clock driver
Maker NXP
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PCKV857 Datasheet PDF






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