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PCK953 Datasheet

50-125 MHz PECL input/9 CMOS output 3.3 V PLL clock driver

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INTEGRATED CIRCUITS
PCK953
50–125 MHz PECL input/9 CMOS output
3.3 V PLL clock driver
Product specification
Supersedes data of 2000 Oct 25
ICL03 — PC Motherboard ICs; Logic Products
Group
2001 Feb 08
Philips
Semiconductors


NXP Semiconductors Electronic Components Datasheet

PCK953 Datasheet

50-125 MHz PECL input/9 CMOS output 3.3 V PLL clock driver

No Preview Available !

Philips Semiconductors
50–125 MHz PECL input/CMOS output
3.3 V PLL clock driver
Product specification
PCK953
DESCRIPTION
The PCK953 is a 3.3 V compatible, PLL-based clock driver device
targeted for high performance clock tree designs. With output
frequencies of up to 125 MHz, and output skews of 100 ps, the
PCK953 is ideal for the most demanding clock tree designs. The
devices employ a fully differential PLL design to minimize
cycle-to-cycle and phase jitter.
The PCK953 has a differential LVPECL reference input, along with
an external feedback input. These features make the PCK953 ideal
for use as a zero delay, low skew fanout buffer. The device
performance has been tuned and optimized for zero delay
performance. The MR/OE input pin will reset the internal counters
and 3-State the output buffers when driven HIGH.
The PCK953 is fully 3.3 V compatible and requires no external loop
filter components. All control inputs accept LVCMOS or LVTTL
compatible levels, while the outputs provide LVCMOS levels with the
ability to drive terminated 50 transmission lines. For series
terminated 50 lines, each of the PCK953 outputs can drive two
traces, giving the device an effective fanout of 1:18. The device is
packaged in a 7 × 7 mm 32-lead LQFP package to provide the
optimum combination of board density and performance.
PIN CONFIGURATION
VCCA 1
FB_CLK 2
NC 3
NC 4
NC 5
NC 6
GNDI 7
PECL_CLK 8
FEATURES
Fully integrated PLL
Output frequency up to 125 MHz in PLL mode
Outputs disable in high impedance
LQFP packaging
55 ps cycle-to-cycle jitter typical
9 mA quiescent current, ICCA, typical
60 ps static phase offset typical
Less than 10 µA quiescent current, lCCO, typical
ORDERING INFORMATION
PACKAGES
plastic low profile quad flat
package; 32 leads
TEMPERATURE RANGE
0 to +70°C
ORDER CODE
PCK953BD
LOGIC DIAGRAM
PECL_CLK
PECL_CLK
FB_CLK
VCO_SEL
BYPASS
MR/OE
PLL_EN
PHASE
DETECTOR
LPF
VCO
200–500 MHz
B4
B2
2001 Feb 08
2
24 Q1
23 VCCO
22 Q2
21 GNDO
20 Q3
19 VCCO
18 Q4
17 GNDO
SW00625
DRAWING NUMBER
SOT358-1
QFB
7
Q0:6
Q7
SW00624
853–2222 25600


Part Number PCK953
Description 50-125 MHz PECL input/9 CMOS output 3.3 V PLL clock driver
Maker NXP
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PCK953 Datasheet PDF






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