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PCK953 Datasheet 50-125 Mhz Pecl Input/9 CMOS Output 3.3 V Pll Clock Driver

Manufacturer: NXP Semiconductors

Overview: INTEGRATED CIRCUITS PCK953 50–125 MHz PECL input/9 CMOS output 3.3 V PLL clock driver Product specification Supersedes data of 2000 Oct 25 ICL03 — PC Motherboard ICs; Logic Products Group 2001 Feb 08 Philips Semiconductors Philips Semiconductors Product specification 50–125 MHz PECL input/CMOS output 3.

General Description

The PCK953 is a 3.3 V patible, PLL-based clock driver device targeted for high performance clock tree designs.

With output frequencies of up to 125 MHz, and output skews of 100 ps, the PCK953 is ideal for the most demanding clock tree designs.

The devices employ a fully differential PLL design to minimize cycle-to-cycle and phase jitter.

Key Features

  • make the PCK953 ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The MR/OE input pin will reset the internal counters and 3-State the output buffers when driven HIGH. The PCK953 is fully 3.3 V compatible and requires no external loop filter components. All control inputs accept LVCMOS or LVTTL compatible levels, while the outputs provide LVCMOS levels with the ability to drive terminated 50 Ω transmission lines.

More Datasheets from NXP Semiconductors

Part Number Description
PCK940L Low voltage 1 : 18 clock distribution chip
PCK942C Low voltage 1 : 18 clock distribution chip
PCK9446 LVCMOS clock fan-out buffer
PCK9447 LVCMOS clock fan-out buffer
PCK9448 LVCMOS 1 : 12 clock fan-out buffer
PCK9456 2.5 V and 3.3 V LVCMOS clock fan-out buffer
PCK946 Low voltage 1 : 10 CMOS clock driver
PCK111 Low voltage 1:10 differential PECL clock driver
PCK12429 25-400 MHz differential PECL clock generator
PCK2000 CK97 66/100MHz System Clock Generator

PCK953 Distributor