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PCK953 - 50-125 MHz PECL input/9 CMOS output 3.3 V PLL clock driver

Description

The PCK953 is a 3.3 V compatible, PLL-based clock driver device targeted for high performance clock tree designs.

With output frequencies of up to 125 MHz, and output skews of 100 ps, the PCK953 is ideal for the most demanding clock tree designs.

Features

  • make the PCK953 ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The MR/OE input pin will reset the internal counters and 3-State the output buffers when driven HIGH. The PCK953 is fully 3.3 V compatible and requires no external loop filter components. All control inputs accept LVCMOS or LVTTL compatible levels, while the outputs provide LVCMOS levels with the ability to drive terminated 50 Ω transmission lines.

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Datasheet Details

Part number PCK953
Manufacturer NXP Semiconductors
File Size 71.10 KB
Description 50-125 MHz PECL input/9 CMOS output 3.3 V PLL clock driver
Datasheet download datasheet PCK953 Datasheet

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Full PDF Text Transcription

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INTEGRATED CIRCUITS PCK953 50–125 MHz PECL input/9 CMOS output 3.3 V PLL clock driver Product specification Supersedes data of 2000 Oct 25 ICL03 — PC Motherboard ICs; Logic Products Group 2001 Feb 08 Philips Semiconductors Philips Semiconductors Product specification 50–125 MHz PECL input/CMOS output 3.3 V PLL clock driver PCK953 DESCRIPTION The PCK953 is a 3.3 V compatible, PLL-based clock driver device targeted for high performance clock tree designs. With output frequencies of up to 125 MHz, and output skews of 100 ps, the PCK953 is ideal for the most demanding clock tree designs. The devices employ a fully differential PLL design to minimize cycle-to-cycle and phase jitter. The PCK953 has a differential LVPECL reference input, along with an external feedback input.
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