PCK953 - 50-125 MHz PECL input/9 CMOS output 3.3 V PLL clock driver

Product Overview

NXP

Part number	PCK953
Manufacturer	NXP
File Size	71.10 KB
Description	50-125 MHz PECL input/9 CMOS output 3.3 V PLL clock driver
Datasheet	PCK953 Datasheet
Additional preview pages of the PCK953 datasheet.

The PCK953 is a 3.3 V compatible, PLL-based clock driver device targeted for high performance clock tree designs.

With output frequencies of up to 125 MHz, and output skews of 100 ps, the PCK953 is ideal for the most demanding clock tree designs.

make the PCK953 ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The MR/OE input pin will reset the internal counters and 3-State the output buffers when driven HIGH. The PCK953 is fully 3.3 V compatible and requires no external loop filter components. All control inputs accept LVCMOS or LVTTL compatible levels, while the outputs provide LVCMOS levels with the ability to drive terminated 50 Ω transmission lines.

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Published: Mar 22, 2005 |