PCK857 Datasheet | NXP Semiconductors

INTEGRATED CIRCUITS PCK857 66- 150MHz Phase Locked Loop Differential 1:10 SDRAM Clock Driver Preliminary specification 1998 Dec 10 Philips Semiconductors Philips Semiconductors Preliminary specification 66- 150MHz Phase Locked Loop Differential 1:10 SDRAM Clock Driver Features - Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications PIN CONFIGURATION GND 1 Y0 2 Y0 3 VDDQ 4 Y1 5 Y1 6 GND 7 GND 8 Y2 9 Y2 10 VDDQ 11 VDDQ 12 CLK 13 CLK 14 VDDQ 15 AVCC 16 AGND 17 GND 18 Y3 19 Y3 20 VDDQ 21 Y4 22 Y4 23 GND 24 48 GND 47 Y5 46 Y5 45 VDDQ 44 Y6 43 Y6 42 GND 41 GND 40 Y7 39 Y7 38 VDDQ 37 G 36 FBIN 35 FBIN 34 VDDQ 33 FBOUT 32 FBOUT 31 GND 30 Y8 29 Y8 28 VDDQ 27 Y9 26 Y9 25 GND - 1-to-10 differential clock distribution - Very low skew (< 100ps) and jitter (< 100ps) - 3V AVCC and 2.5V Vddq - SSTL_2 interface clock inputs and outputs - CMOS control signal input - Test mode enables buffers while disabling PLL - Low current power-down mode - Tolerant of Spread Spectrum input clock - Full DDR solution provided when used with SSTL16857 and CBT3857 DESCRIPTION Zero delay buffer to distribute an SSTL differential clock input pair to 10 SSTL_2 differential output pairs. Outputs are slope controlled. External feedback pin for synchronization of the outputs to the input. A CMOS style Enable/Disable pin is provided for low power disable. SW00358 ORDERING INFORMATION PACKAGES 48-Pin Plastic TSSOP TEMPERATURE RANGE 0°C to +70°C OUTSIDE NORTH AMERICA PCK857 DGG NORTH AMERICA PCK857 DGG DRAWING NUMBER SOT362-1 PINS 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 2, 3, 5, 6, 9, 10, 19, 20, 22, 23, 26, 27, 29, 30, 32, 33, 39, 40, 43, 44, 46, 47 4, 11, 12, 15, 21, 28, 34 13, 14, 35, 36 16 17 37 SYMBOL GND Yn, Ynb, FBOUT, FBOUTb VDDQ CLKIN, CLKINb, FBIN, FBINb AVCC AGND G DESCRIPTION SSTL_2 ground pins SSTL_2 differential outputs SSTL_2 power pins SSTL_2 differential inputs Analog power Analog ground Power-down control...