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PCK2510SL - 50-150 MHz 1:10 SDRAM clock driver

Datasheet Summary

Description

The PCK2510SL is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver.

It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs.

Features

  • Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM.

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Datasheet preview – PCK2510SL

Datasheet Details

Part number PCK2510SL
Manufacturer NXP
File Size 78.53 KB
Description 50-150 MHz 1:10 SDRAM clock driver
Datasheet download datasheet PCK2510SL Datasheet
Additional preview pages of the PCK2510SL datasheet.

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Full PDF Text Transcription

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INTEGRATED CIRCUITS PCK2510SL 50–150 MHz 1:10 SDRAM clock driver Product specification ICL03 — PC Motherboard ICs; Logic Products Group 2000 Dec 01 Philips Semiconductors Philips Semiconductors Product specification 50–150 MHz 1:10 SDRAM clock driver PCK2510SL FEATURES • Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM applications independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the PCK2510SL does not require external RC networks.
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