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PCK2510S Datasheet

50-150 MHz 1:10 SDRAM clock driver

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INTEGRATED CIRCUITS
PCK2510S
50–150 MHz 1:10 SDRAM clock driver
Product specification
1999 Dec 13
Philips
Semiconductors


NXP Semiconductors Electronic Components Datasheet

PCK2510S Datasheet

50-150 MHz 1:10 SDRAM clock driver

No Preview Available !

Philips Semiconductors
50–150 MHz 1:10 SDRAM clock driver
Product specification
PCK2510S
FEATURES
Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM
applications
Spread Spectrum clock compatible
Operating frequency 50 to 150 MHz
(tphase error – jitter) at 100 to133 MHz = ±50 ps
Jitter (peak-peak) at 100 to 133 MHz = ± 80 ps
Jitter (cycle-cycle) at 100 to 133 MHz = 65 ps
Pin-to-pin skew < 200 ps
Available in plastic 24-Pin TSSOP
Distributes one clock input to one bank of ten outputs
External Feedback (FBIN) terminal Is used to synchronize the
outputs to the clock input
On-Chip series damping resistors
No external RC network required
Operates at 3.3 V
DESCRIPTION
The PCK2510S is a high-performance, low-skew, low-jitter,
phase-locked loop (PLL) clock driver. It uses a PLL to precisely
align, in both frequency and phase, the feedback (FBOUT) output to
the clock (CLK) input signal. It is specifically designed for use with
synchronous DRAMs. The PCK2510S operates at 3.3 V VCC and is
input compatible with both 2.5 V and 3.3 V input voltage ranges. It
also provides integrated series damping resistors that make it ideal
for driving point-to-point loads.
One bank of ten outputs provides ten low-skew, low-jitter copies of
CLK. Output signal duty cycles are adjusted to 50 percent,
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
24-Pin Plastic TSSOP
0°C to +70°C
independent of the duty cycle at CLK. All outputs can be enabled or
disabled via a single output enable input. When the G input is high,
the outputs switch in phase and frequency with CLK; when the G
input is low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the PCK2510S does not
require external RC networks. The loop filter for the PLL is included
on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the PCK2510S requires a
stabilization time to achieve phase lock of the feedback signal to the
reference signal. This stabilization time is required, following power
up and application of a fixed-frequency, fixed-phase signal at CLK,
and following any changes to the PLL reference. The PLL can be
bypassed for test purposes by strapping AVCC to ground.
The PCK2510S is characterized for operation from 0°C to +70°C.
PIN CONFIGURATION
AGND 1
VCC 2
1Y0 3
1Y1 4
1Y2 5
GND 6
GND 7
1Y3 8
1Y4 9
VCC 10
G 11
FBOUT 12
24 CLK
23 AVCC
22 VCC
21 1Y9
20 1Y8
19 GND
18 GND
17 1Y7
16 1Y6
15 1Y5
14 VCC
13 FBIN
SW00382
ORDER CODE
PCK2510S PW
DRAWING NUMBER
SOT355-1
1999 Dec 13
2 853–2184 22832


Part Number PCK2510S
Description 50-150 MHz 1:10 SDRAM clock driver
Maker NXP
PDF Download

PCK2510S Datasheet PDF






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