PCK2509SA 50-150 MHz 1:9 SDRAM clock driver
• Phase-Locked Loop Clock distribution for
PC100/PC133 SDRAM applications
• JEDEC compliant operation—PLL reamins locked when outputs
are disabled.
adjusted to.
• JEDEC compliant operation—PLL reamins locked when outputs
are disabled.
adjusted to 50 percent, independent of t.
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