Datasheet4U Logo Datasheet4U.com

PCK2509SA - 50-150 MHz 1:9 SDRAM clock driver

Description

The PCK2509SA is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver.

It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs.

Features

  • Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
PCK METALLIZED POLYPROPYLENE FILM CAPACITORS Rubycon
PCK0E122MCO1GS CONDUCTIVE POLYMER ALUMINUM SOLID ELECTROLYTIC CAPACITORS Nichicon
PCK0E222MCO1GS CONDUCTIVE POLYMER ALUMINUM SOLID ELECTROLYTIC CAPACITORS Nichicon
PCK0E391MCO1GS CONDUCTIVE POLYMER ALUMINUM SOLID ELECTROLYTIC CAPACITORS Nichicon
PCK0E561MCO1GS CONDUCTIVE POLYMER ALUMINUM SOLID ELECTROLYTIC CAPACITORS Nichicon

Other Datasheets by NXP Semiconductors

Part Number Description
PCK2509S 50-150 MHz 1:9 SDRAM clock driver
PCK2509SL 50-150 MHz 1:9 SDRAM clock driver
PCK2510S 50-150 MHz 1:10 SDRAM clock driver
PCK2510SA 50-150 MHz 1:10 SDRAM clock driver
PCK2510SL 50-150 MHz 1:10 SDRAM clock driver

Full PDF Text Transcription

Click to expand full text
INTEGRATED CIRCUITS PCK2509SA 50–150 MHz 1:9 SDRAM clock driver Product specification ICL03 — PC Motherboard ICs; Logic Products Group 2000 Dec 01 Philips Semiconductors Philips Semiconductors Product specification 50–150 MHz 1:9 SDRAM clock driver PCK2509SA FEATURES • Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM applications • JEDEC compliant operation—PLL reamins locked when outputs are disabled. adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic–low state.
Published: |