PCK2509S Description
The PCK2509S is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLLto precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs.
PCK2509S Key Features
- Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM