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PCK2509S - 50-150 MHz 1:9 SDRAM clock driver

Datasheet Summary

Description

The PCK2509S is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver.

It uses a PLLto precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs.

Features

  • Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM.

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Datasheet Details

Part number PCK2509S
Manufacturer NXP
File Size 70.65 KB
Description 50-150 MHz 1:9 SDRAM clock driver
Datasheet download datasheet PCK2509S Datasheet
Additional preview pages of the PCK2509S datasheet.

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Full PDF Text Transcription

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INTEGRATED CIRCUITS PCK2509S 50–150 MHz 1:9 SDRAM clock driver Product specification 1999 Oct 19 Philips Semiconductors Philips Semiconductors Product specification 50–150 MHz 1:9 SDRAM clock driver PCK2509S FEATURES • Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM applications • Spread Spectrum clock compatible • Operating frequency 50 to 150 MHz • (tphase error – jitter) at 100 to133 MHz = ±50 ps • Jitter (peak-peak) at 100 to 133 MHz = ± 80 ps • Jitter (cycle-cycle) at 100 to 133 MHz = 65 ps • Pin-to-pin skew < 200 ps • Available in plastic 24-Pin TSSOP • Distributes one clock input to one bank of ten outputs • External Feedback (FBIN) terminal Is used to synchronize the outputs to the clock input adjusted to 50 percent, independent of the duty cycle at CLK.
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