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PCK111 Datasheet

Low voltage 1:10 differential PECL clock driver

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INTEGRATED CIRCUITS
PCK111
Low voltage 1:10 differential
PECL clock driver
Product data
File under Integrated Circuits — ICL03
2001 Sep 07
Philips
Semiconductors


NXP Semiconductors Electronic Components Datasheet

PCK111 Datasheet

Low voltage 1:10 differential PECL clock driver

No Preview Available !

Philips Semiconductors
Low voltage 1:10 differential
PECL clock driver
Product data
PCK111
FEATURES
100 ps part-to-part skew typical
35 ps output-to-output skew typical
Differential design
VBB output
Low voltage VCC range of +2.375 V to +3.8 V for PECL
75 kinput pull-down resistors
ECL/PECL outputs
Form, fit, and function compatible with MC100EP111
DESCRIPTION
The PCK111 is a low skew 1-to-10 differential driver, designed with
clock distribution in mind. It accepts two clock sources into an input
multiplexer. The PECL input signals can be either differential or
single-ended if the VBB output is used. The selected signal is fanned
out to 10 identical differential outputs.
The PCK111 is specifically designed, modeled and produced with
low skew as the key goal. Optimal design and layout serve to
minimize gate-to-gate skew within a device, and empirical modeling
is used to determine process control limits that ensure consistent
tPD distributions from lot to lot. The net result is a dependable,
guaranteed low skew device.
To ensure that the tight skew specification is met, it is necessary that
both sides of the differential output are terminated into 50 , even if
only one side is being used. In most applications, all ten differential
pairs will be used, and therefore terminated. In the case where fewer
than ten pairs are used, it is necessary to terminate at least the
output pairs on the same package side as the pair(s) being used on
that side, in order to maintain minimum skew. Failure to do this will
result in small degradations of propagation delay (on the order of
10–20 ps) of the output(s) being used, which, while not being
catastrophic to most designs, will mean a loss of skew margin.
The PCK111 can be used for high performance clock distribution in
+3.3 V or +2.5 V systems. Designers can take advantage of the
PCK111’s performance to distribute low skew clocks across the
backplane or the board. In a PECL environment, series or Thevenin
line terminations are typically used as they require no additional
power supplies.
The PCK111 may be driven single-endedly utilizing the VBB bias
output with the CLK0 input. If a single-ended signal is to be used,
the VBB pin should be connected to the CLK0 input and bypassed to
ground via a 0.01 µF capacitor. The VBB output can only source/sink
0.2 mA, therefore, it should be used as a switching reference for the
PCK111 only. Part-to-part skew specifications are not guaranteed
when driving the PCK111 single-endedly.
PINNING
Pin configuration
VCC 1
CLK_SEL 2
CLK0 3
CLK0 4
VBB 5
CLK1 6
CLK1 7
VEE 8
PCK111
24 Q3
23 Q3
22 Q4
21 Q4
20 Q5
19 Q5
18 Q6
17 Q6
Figure 1. Pin configuration
SW00907
Pin description
SYMBOL
PIN
DESCRIPTION
VCC
CLK_SEL
1
2
Supply voltage
Active clock select input
CLK0, CLK0 3, 4
Differential ECL/PECL input pair
VBB
CLK1, CLK1
5
6, 7
VBB output
Differential HSTL input pair
VEE
VCCO
8
9, 16, 25, 32
Ground
Output drive power supply
voltage
Q0–Q9
31, 29, 27, 24, Differential PECL outputs
22, 20, 18, 15,
13, 11
Q0–Q9
30, 28, 26, 23, Differential PECL outputs
21, 19, 17, 14,
12, 10
ORDERING INFORMATION
Type number
Package
Name
Description
PCK111BD
LQFP32
plastic low profile quad flat package; 32 leads; body 7 × 7 × 1.4 mm
Version
SOT358-1
Temperature
range
–40 to +70 °C
2001 Sep 07
2 853-2281 27052


Part Number PCK111
Description Low voltage 1:10 differential PECL clock driver
Maker NXP
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PCK111 Datasheet PDF






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