PCD5090
Overview
This data sheet details the specific features of the: PCD5090/xxx; DSP-ROM, with external ROM PCA5097/xxx; DSP-ROM, with Field Electronically Erasable Programmable Read Only Memory (FEEPROM). PCD5090; PCA5097 On-chip reference voltage FEATURES General The PCx509x is designed for GAP-compliant handsets and simple base stations Embedded 80C51 microcontroller with twice the performance of the classic architecture, up to 128 kbytes external memory or 64 kbytes FEEPROM program memory and 3 kbytes of data memory on chip.
- On-chip reference voltage FEATURES General
- The PCx509x is designed for GAP-compliant handsets and simple base stations
- Embedded 80C51 microcontroller with twice the performance of the classic architecture, up to 128 kbytes external memory or 64 kbytes FEEPROM program memory and 3 kbytes of data memory on chip. In addition there is 1 kbyte of on-chip data memory that is shared with on-chip Burst Mode Logic (BML) and DSP, the System Data RAM (SDR).
- 80C51 ports P0, P1, P2 and P3 available for interfacing to display, keyboard, I2C-bus, interrupt sources and/or external memory. External program memory is addressable up to 128 kbytes (PCD5090/xxx and PCA5097/xxx).
- Portable Part (PP) and Fixed Part (FP) modes
- TDMA frame (de)multiplexing; transmission or reception can be programmed for any slot
- Ciphering, scrambling, CRC checking/generation, protected B-fields
- Speech and data buffering space for six handsets
- Local call and B-field loop-back
- Two interrupt lines for BML and DSP to interrupt 80C51
