PCD5002 Description
ORDERING INFORMATION LICENSE BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Introduction The POCSAG paging code The APOC-1 paging code Error correction Operating states ON status OFF status Reset Bit rates Oscillator Input data processing Battery saving POCSAG Synchronization strategy APOC-1 synchronization strategy Call termination Call data output format Error type indication Data transfer Continuous data decoding...
PCD5002 Applications
- On-chip SRAM buffer for message data
- Slave I2C-bus interface to microcontroller for transfer of message data, status/control and EEPROM programming (data transfer at up to 100 kbits/s)
- Wake-up interrupt for microcontroller, programmable polarity