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PCD5002 Datasheet Advanced POCSAG and APOC-1 Paging Decoder

Manufacturer: NXP Semiconductors

General Description

ORDERING INFORMATION LICENSE BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Introduction The POCSAG paging code The APOC-1 paging code Error correction Operating states ON status OFF status Reset Bit rates Oscillator Input data processing Battery saving POCSAG Synchronization strategy APOC-1 synchronization strategy Call termination Call data output format Error type indication Data transfer Continuous data decoding Receiver and oscillator control External receiver control and monitoring Battery condition input Synthesizer control Serial microcontroller interface Decoder I2C-bus access External interrupt Status/Control register Pending interrupts Out-of-range indication Real time clock Periodic interrupt Received call delay Alert generation Alert cadence register (03H;

write) Acoustic alert Vibrator alert LED alert Warbled alert Direct alert control Alert priority 8.41 8.42 8.43 8.44 8.45 8.46 8.47 8.48 8.49 8.50 8.51 8.52 8.53 8.54 8.55 8.56 8.57 8.58 8.59 8.60 8.61 9 9.1 9.2 9.3 9.4 10 11 12 13 14 15 16 17 17.1 17.2 17.3 17.4 18 19 20 PCD5002 Cancelling alerts Automatic POCSAG alerts SRAM access RAM write address pointer (06H;

read) RAM read address pointer (08H;

Overview

INTEGRATED CIRCUITS DATA SHEET PCD5002 Advanced POCSAG and APOC-1 Paging Decoder Product specification Supersedes data of 1997 Mar 04 File under Integrated Circuits, IC17 1997 Jun 24 Philips Semiconductors Product specification Advanced POCSAG and APOC-1 Paging Decoder CONTENTS 1 2 3 4 5 6 7 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.18 8.19 8.20 8.21 8.22 8.23 8.24 8.25 8.26 8.27 8.28 8.29 8.30 8.31 8.32 8.33 8.34 8.35 8.36 8.37 8.38 8.39 8.