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PCA5010 - Pager baseband controller

General Description

BLOCK DIAGRAM PINNING INFORMATION FUNCTIONAL DESCRIPTION General CPU timing Overview on the different clocks used within the PCA5010 Memory organization Addressing I/O facilities Timer/event counters I2C-bus serial I/O Serial interface SIO0: UART 76.8 kHz oscillator Clock correction 6 MHz oscillator

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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INTEGRATED CIRCUITS DATA SHEET PCA5010 Pager baseband controller Product speciļ¬cation File under Integrated Circuits, IC17 1998 Nov 02 Philips Semiconductors Product speciļ¬cation Pager baseband controller CONTENTS 1 2 3 4 5 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.20 6.21 6.22 7 7.1 8 9 10 11 12 13 FEATURES ORDERING INFORMATION GENERAL DESCRIPTION BLOCK DIAGRAM PINNING INFORMATION FUNCTIONAL DESCRIPTION General CPU timing Overview on the different clocks used within the PCA5010 Memory organization Addressing I/O facilities Timer/event counters I2C-bus serial I/O Serial interface SIO0: UART 76.