8-bit microcontroller with accelerated two-clock 80C51 core
2.2 Additional features
A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns
for all instructions except multiply and divide when executing at 18 MHz. This is six
times the performance of the standard 80C51 running at the same clock frequency. A
lower clock frequency for the same performance results in power savings and reduced
Serial flash In-Circuit Programming (ICP) allows simple production coding with
commercial EPROM programmers. Flash security bits prevent reading of sensitive
Serial flash In-System Programming (ISP) allows coding while the device is mounted
in the end application.
In-Application Programming (IAP) of the flash code memory. This allows changing the
code in a running application.
Watchdog timer with separate on-chip oscillator, nominal 400 kHz, calibrated to ±5 %,
requiring no external components. The watchdog prescaler is selectable from
High-accuracy internal RC oscillator option, with clock doubler option, allows operation
without external oscillator components. The RC oscillator option is selectable and fine
Switching on the fly among internal RC oscillator, watchdog oscillator, external clock
source provides optimal support of minimal power active mode with fast switching to
Idle and two different power-down reduced power modes. Improved wake-up from
Power-down mode (a LOW interrupt input starts execution). Typical power-down
current is 1 μA (total power-down with voltage comparators disabled).
Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A software reset function is also available.
Configurable on-chip oscillator with frequency range options selected by user
programmed flash configuration bits. Oscillator options support frequencies from
20 kHz to the maximum operating frequency of 18 MHz.
Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator
allowing it to perform an oscillator fail detect function.
Programmable port output configuration options: quasi-bidirectional, open drain,
High current sourcing/sinking (20 mA) on eight I/O pins (P0.3 to P0.7, P1.4, P1.6,
P1.7). All other port pins have high sinking capability (20 mA). A maximum limit is
specified for the entire chip.
Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of
the pins match or do not match a programmable pattern.
Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns
minimum ramp times.
Only power and ground connections are required to operate the P89LPC9321 when
internal reset option is selected.
Four interrupt priority levels.
Eight keypad interrupt inputs, plus two additional external interrupt inputs.
Schmitt trigger port inputs.
Second data pointer.
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 November 2010
© NXP B.V. 2010. All rights reserved.
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