P89LPC9301 Datasheet | NXP Semiconductors

.. P89LPC9301/931A1 8-bit microcontroller with accelerated two-clock 80C51 core 4 k B/8 k B 3 V byte-erasable flash Rev. 01 - 9 April 2009 Preliminary data sheet 1. General description The P89LPC9301/931A1 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC9301/931A1 in order to reduce ponent count, board space, and system cost. 2. Features 2.1 Principal Features I 4 k B/8 k B byte-erasable flash code memory organized into 1 k B sectors and 64-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage. I 256-byte RAM data memory. I Two analog parators with selectable inputs and reference source. I Two 16-bit counter/timers (each may be configured to toggle a port output upon timer overflow or to bee a PWM output). I A 23-bit system timer that can also be used as real-time clock consisting of a 7-bit prescaler and a programmable and readable 16-bit timer. I Enhanced UART with a fractional baud rate generator, break detect, framing error detection, and automatic address detection; 400 k Hz byte-wide I2C-bus munication port and SPI munication port. I 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or driven to 5.5 V). I Enhanced low voltage (brownout) detect allows a graceful system shutdown when power fails. I 28-pin TSSOP and PLCC packages with 23 I/O pins minimum and up to 26 I/O pins while using on-chip oscillator and reset options. 2.2 Additional Features I A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz. This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance...