P80CL31
FEATURES
GENERAL DESCRIPTION
Versions: P80CL31 and P80C51 APPLICATIONS ORDERING INFORMATION BLOCK DIAGRAM FUNCTIONAL DIAGRAM PINNING INFORMATION Pinning Pin description
FUNCTIONAL DESCRIPTION
OVERVIEW
General CPU timing MEMORY ORGANIZATION Program Memory Data Memory Special Function Registers (SFRs) Addressing I/O FACILITIES Ports Port options Port 0 options SET/RESET options TIMERS/EVENT COUNTERS REDUCED POWER MODES Idle mode Power-down mode Wake-up from Power-down mode Power Control Register (PCON) Status of external pins STANDARD SERIAL INTERFACE SIO0: UART Multiprocessor munications Serial Port Control and Status Register (S0CON) 25 26 26.1 26.2 26.3 27 28 13.3 14 14.1 14.2 14.3 15 16 16.1 16.2 17 17.1 17.2 18 19 20 21 22 23 24 24.1 24.2 24.3 Baud rates
P80CL31; P80CL51
INTERRUPT SYSTEM External interrupts INT2 to INT9 Interrupt priority Interrupt registers OSCILLATOR CIRCUITRY RESET External reset using the RST pin Power-on-reset MASK OPTIONS FOR P80CL31 AND P80C51 P80CL31:...
