• Part: NX5DV330
  • Description: Quad 1-of-2 video multiplexer/demultiplexer
  • Manufacturer: NXP Semiconductors
  • Size: 86.13 KB
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NXP Semiconductors
NX5DV330
NX5DV330 is Quad 1-of-2 video multiplexer/demultiplexer manufactured by NXP Semiconductors.
description The NX5DV330 is a quad 1-of-2 high-speed TTL-patible video multiplexer/demultiplexer. The low ON resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise It has a digital select input (S), four independent inputs/outputs (n Y0, n Y1), a mon input/output (n Z) and an active LOW enable input (E). When pin E is HIGH, the switch is turned off. Schmitt-trigger action at the enable input (E) and select input (S) makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 4.0 V to 5.5 V. The NX5DV330 is characterized for operation from - 40 °C to +85 °C. 2. Features I 5 Ω switch connection between two ports I TTL-patible input levels I Minimal propagation delay through the switch I ESD protection: N HBM JESD22-A114E Class 2A exceeds 2000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 m A NXP Semiconductors Quad 1-of-2 video multiplexer/demultiplexer 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description NX5DV330D - 40 °C to +85 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm NX5DV330DS - 40 °C to +85 °C SSOP16[1] plastic shrink small outline package; 16 leads; body width 3.9 mm; lead pitch 0.635 mm NX5DV330PW - 40 °C to +85 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm NX5DV330BQ - 40 °C to +85 °C DHVQFN16 plastic dual in-line patible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm Version SOT109-1 SOT519-1 SOT403-1 SOT763-1 [1] Also known as QSOP16. 4. Functional diagram 1Z 4 2Z 7 3Z 9 12 4Z 2 1Y0 3 1Y1 5 2Y0 6 2Y1 11 3Y0 10 3Y1 14 4Y0 13 4Y1 Fig 1. Logic diagram S1...