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NPIC6C596 - Power logic 8-bit shift register

Description

The NPIC6C596 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and open-drain outputs.

Both the shift and storage register have separate clocks.

Features

  • Specified from 40 C to +125 C.
  • Low RDSon.
  • Eight Power EDNMOS transistor outputs of 100 mA continuous current.
  • 250 mA current limit capability.
  • Output clamping voltage 33 V.
  • 30 mJ avalanche energy capability.
  • Enhanced cascading for multiple stages.
  • All registers cleared with single input.
  • Low power consumption.
  • ESD protection:.
  • HBM JDS-001 Class 2 exceeds 2500 V.
  • CDM JESD22-C101E exceeds 1000 V NXP Semiconductors NPIC6C596 Power lo.

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Other Datasheets by NXP Semiconductors

Part Number Description
NPIC6C596A Power logic 8-bit shift register
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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NPIC6C596 Power logic 8-bit shift register; open-drain outputs Rev. 2 — 4 July 2013 Product data sheet 1. General description The NPIC6C596 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and open-drain outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR resets both the shift register and storage register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register is always one clock pulse ahead of the storage register.
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