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NXP Semiconductors Electronic Components Datasheet

MIMXRT1052DVL6A Datasheet

i.MX RT1050 Crossover Processors

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NXP Semiconductors
Data Sheet: Technical Data
Document Number: IMXRT1050CEC
Rev. 1.3, 03/2019
i.MX RT1050 Crossover
Processors Data Sheet
for Consumer Products
MIMXRT1051DVL6A
MIMXRT1051DVL6B
MIMXRT1051DVJ6B
MIMXRT1052DVL6A
MIMXRT1052DVL6B
MIMXRT1052DVJ6B
Package Information
Plastic Package
196-pin MAPBGA, 10 x 10 mm, 0.65 mm pitch
196-pin MAPBGA, 12 x 12 mm, 0.8 mm pitch
Ordering Information
1 i.MX RT1050 introduction
See Table 1 on page 5
The i.MX RT1050 is a new processor family featuring 1. i.MX RT1050 introduction . . . . . . . . . . . . . . . . . . . . . . . . 1
NXP’s advanced implementation of the Arm
Cortex®-M7 core, which operates at speeds up to 600
MHz to provide high CPU performance and best
1.1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 5
2. Architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
real-time response.
3. Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1. Special signal considerations . . . . . . . . . . . . . . . 15
The i.MX RT1050 processor has 512 KB on-chip RAM,
3.2. Recommended connections for unused analog
interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
which can be flexibly configured as TCM or
4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 18
general-purpose on-chip RAM. The i.MX RT1050
integrates advanced power management module with
4.1. Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . 18
4.2. System power and clocks . . . . . . . . . . . . . . . . . . 25
4.3. I/O parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DCDC and LDO that reduces complexity of external
power supply and simplifies power sequencing. The
i.MX RT1050 also provides various memory interfaces,
4.4. System modules . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.5. External memory interface . . . . . . . . . . . . . . . . . 41
4.6. Display and graphics . . . . . . . . . . . . . . . . . . . . . . 51
4.7. Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
including SDRAM, RAW NAND FLASH, NOR
FLASH, SD/eMMC, Quad SPI, and a wide range of
4.8. Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.9. Communication interfaces . . . . . . . . . . . . . . . . . . 64
4.10. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
other interfaces for connecting peripherals, such as
5. Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 79
WLAN, Bluetooth™, GPS, displays, and camera
5.1. Boot mode configuration pins . . . . . . . . . . . . . . . 79
5.2. Boot device interface allocation . . . . . . . . . . . . . . 79
sensors. The i.MX RT1050 also has rich audio and video 6. Package information and contact assignments . . . . . . . 84
features, including LCD display, basic 2D graphics,
camera interface, SPDIF, and I2S audio interface. The
6.1. 10 x 10 mm package information . . . . . . . . . . . . 84
6.2. 12 x 12 mm package information . . . . . . . . . . . . 96
7. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
NXP reserves the right to change the production detail specifications as may be required
to permit improvements in the design of its products.


NXP Semiconductors Electronic Components Datasheet

MIMXRT1052DVL6A Datasheet

i.MX RT1050 Crossover Processors

No Preview Available !

i.MX RT1050 introduction
i.MX RT1050 has analog interfaces, such as ADC, ACMP, and TSC.
The i.MX RT1050 is specifically useful for applications such as:
• Industrial Human Machine Interfaces (HMI)
• Motor Control
• Home Appliance
1.1 Features
The i.MX RT1050 processors are based on Arm Cortex-M7 MPCore™ Platform, which has the
following features:
• Supports single Arm Cortex-M7 MPCore with:
— 32 KB L1 Instruction Cache
— 32 KB L1 Data Cache
— Full featured Floating Point Unit (FPU) with support of the VFPv5 architecture
— Support the Armv7-M Thumb instruction set
• Integrated MPU, up to 16 individual protection regions
• Up to 512 KB I-TCM and D-TCM in total
• Frequency of 600 MHz
• Cortex M7 CoreSight™ components integration for debug
• Frequency of the core, as per Table 10, "Operating ranges," on page 20.
The SoC-level memory system consists of the following additional components:
— Boot ROM (96 KB)
— On-chip RAM (512 KB)
– Configurable RAM size up to 512 KB shared with M7 TCM
• External memory interfaces:
— 8/16-bit SDRAM, up to SDRAM-166
— 8/16-bit SLC NAND FLASH, with ECC handled in software
— SD/eMMC
— SPI NOR FLASH
— Parallel NOR FLASH with XIP support
— Single/Dual channel Quad SPI FLASH with XIP support
• Timers and PWMs:
— Two General Programmable Timers (GPT)
– 4-channel generic 32-bit resolution timer
– Each support standard capture and compare operation
— Four Periodical Interrupt Timer (PIT)
– Generic 16-bit resolution timer
– Periodical interrupt generation
i.MX RT1050 Crossover Processors Data Sheet for Consumer Products, Rev. 1.3, 03/2019
2 NXP Semiconductors


Part Number MIMXRT1052DVL6A
Description i.MX RT1050 Crossover Processors
Maker NXP
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MIMXRT1052DVL6A Datasheet PDF






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