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LPC18S10 - 32-bit ARM Cortex-M3 flashless MCU

Download the LPC18S10 datasheet PDF. This datasheet also covers the LPC18S50 variant, as both devices belong to the same 32-bit arm cortex-m3 flashless mcu family and are provided as variant models within a single manufacturer datasheet.

General Description

The LPC18S50/S30/S10 are ARM Cortex-M3 based microcontrollers with security

Key Features

  • Processor core.
  • ARM Cortex-M3 processor, running at frequencies of up to 180 MHz.
  • ARM Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions.
  • ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
  • Non-maskable Interrupt (NMI) input.
  • JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points.
  • Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
  • System tick timer.
  • On-chip mem.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (LPC18S50-NXP.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by NXP Semiconductors

Part Number Description
LPC18S30 32-bit ARM Cortex-M3 flashless MCU
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
LPC18S50/S30/S10 32-bit ARM Cortex-M3 flashless MCU with security features; up to 200 kB SRAM; Ethernet, two HS USB, LCD, EMC, AES Rev. 1.3 — 10 January 2020 Product data sheet 1. General description The LPC18S50/S30/S10 are ARM Cortex-M3 based microcontrollers with security features for embedded applications. The ARM Cortex-M3 is a next generation core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration. The LPC18S50/S30/S10 operate at CPU frequencies of up to 180 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals.